Embedded Solutions Page 9
has been transferred. If preferred, the TX status can be polled and the transmitter
status determined. Each transmitter channel is independent of the other transmitter
channels.
To receive data another transmitter in the system sends data on the bus, which is
connected, to the IP-429. There are up to eight receive channels per IP-429-II and
each channel can be connected to a different ARINC 429 bus. The Receiver channels
are controlled in pairs for the clock speed. When data is received, an interrupt can be
generated to the host. The interrupt to the host is the ‘OR’ of the interrupt requests from
all of the channels. Each channel has an interrupt mask. There is a status register to
allow the host to determine the cause of the interrupt and to set priorities for responding
to the interrupt(s). The interface can be operated in a polled mode by reading the status
register.
If the system needs to know when data was received, Time Tagging can be useful. IP-
429-II supports Time Tagging by providing a 32 bit counter, which operates at 1 MHz to
provide a 1 uS Time Tag count. When the interrupt from any of the receive channels is
asserted the current “time” is registered into one of eight Time Tag registers. The
software can access the registers to read the count. The time should be read before
another interrupt is generated on that channel or the time will be updated for the new
interrupt. The counter is resettable to allow synchronization with a system timer. With
32 bits, the counter will roll over after ~71.58 minutes.
The Time Tag registers are internal to the Xilinx and are loaded automatically. The
registers are aligned to allow reading as longwords – using the automatic double reads
built into Dynamic Engineering carriers.
