Embedded Solutions Page 13
Register Definitions
IP429II_BASE_REG0
[$00 429 Control Register Port read/write
CONTROL REGISTER 0
DATA BIT
DESCRIPTION
7
Send4 0 = tx disabled, 1 = enabled ch3
6
Send3 0 = tx disabled, 1 = enabled ch2
5
Send2 0 = tx disabled, 1 = enabled ch1
4
Send1 0 = tx disabled, 1 = enabled ch0
3
spare
2
CLR_CNT 0 = run, 1 = clear
1
INT_SET 0 = no interrupt, 1 = force interrupt
0
Clock Speed 0 = 8Mhz, 1 = 32 MHz.
FIGURE 2
IP-429 CONTROL REGISTER 0 BIT MAP
The Clock Speed bit is used to select either the 8 MHz or 32 MHz. IP Clock rate. The
Clock Speed selection defaults to 8 MHz. = 0. The selection should match the IP
reference clock rate to insure proper operation.
This is a legacy bit retained for software
commonality but has no effect on operation.
INT_SET is used to force an interrupt condition to occur. This control bit is useful for
SW development and HW testing. Default to no interrupt = 0, force interrupt with 1.
CLR_CNT is used to reset the 32 bit Time Stamp counter. The clear bit is written with a
1 and then released with a 0 to set the counter to a 0 value and restore operation.
Please refer to the Time Stamp registers for more information.
The Send bits are used to enable the transmitter sections to send when ready. The
transmitters are ready to send when there is data in the output FIFO. The Sendx bit
should be held in the disabled state if more than one word is to be placed into the output
FIFO. If only one word is to be sent each time the Sendx bit can be left enabled and the
data will automatically be transferred when LD2 is accessed with the second write.
