158004.B00
49
Disks has documented sample code illustrating the use of the watchdog function, and
also includes the data sheet of the X5043. Note that it is the responsibility of the user
to design code that will reliably kick the watchdog timer.
The BIOS includes code that disables the watchdog timer immediately after a reset,
and thus if a watchdog time-out occurs the watchdog timer is disabled until after the
operating system is loaded and the application software re-enables it. See section 6.9
for further information on the watchdog timer.
The watchdog timer is disabled prior to entering Standby or Suspend modes. After
resuming operation the watchdog timer is restored to its previous state.
5.3
RESET SWITCH
The TP400 can be reset by issuing a low going pulse on the /RESET line of the J4
connector. In this way a system reset can be generated by an external signal or
switch. The reset switch connects between J4 pins 23 and 24. (Pin 24 is the /RESET
input, and pin 23 is a GND pin). The TP400 will then force the RESETDRV signal on
the PC/104 bus and the PCIRST# signal on the PC/104-Plus bus to be asserted.
The TCDEVPLUS has a push button switch connected between /RESET and GND.
Pressing this switch momentarily will reset the system.
5.4
RESETTING THE PC/104 AND PC/104-Plus BUSES
The TP400 always resets the PC/104 and PC/104-Plus buses whenever the X5043 is
driving the TP400 on-board reset signal - that is, in response to a power failure,
watchdog timer time-out, or a low going pulse on the /RESET line of the J4 I/O
connector.
It is not possible to reset the TP400 by driving the RESETDRV signal on the PC/104
bus or the PCIRST# signal on the PC/104-Plus bus.
Содержание 104-plus
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Страница 136: ...J2 164004 C03 FIGURE J1 TP400ET MECHANICAL DRAWINGS FIGURE J2 TP400ET CIRCUIT DIAGRAM ...
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