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Hercules-EBX CPU User Manual V1.02 Page 99
14. COUNTER/TIMER OPERATION
Hercules-EBX models with Data Acquisition contain two counter/timers that provide various timing
functions on the board for A/D timing and user functions. These counters are controlled with
registers in the on-board data acquisition controller FPGA. See pages 67 and 70 for information
on the counter/timer control register bits and how to perform various functions using these
counters.
14.1 Counter 0 – A/D Sample Control
The first counter, Counter 0, is a 24-bit “divide-by-n” counter used for controlling A/D sampling.
The counter has an internal clock input, an external gate input (“Gate 0” – alternate function for
DIO Channel E bit 4), and a dedicated output (“TOUT 0”). The input is a 10MHz or 100 kHz clock
provided on the board and selected with bit CKFRQ0 in Page 0 Base + 12 bit 0. The gate is an
optional signal that can be input on pin 40 of the I/O header J8 when DIOCTR1 (Page 0: Base +
12 bit 5) is 1. If this signal is not used, then the counter runs freely. The “TOUT 0” signal output is
a positive pulse whose frequency is equal to the input clock divided by the 24-bit divisor
programmed into the counter. The output is always present on pin 42 of the I/O header J8.
The counter operates by counting down from the programmed divisor value. When it reaches
zero, it outputs a positive-going pulse equal to one input clock period (100ns or 10
µ
s, depending
on the input clock selected by CKFRQ0). It then reloads to the initial load value and repeats the
process indefinitely.
The output frequency can range from 5MHz (10MHz clock, divisor = 2) down to 0.006Hz (100 kHz
clock divided by 16,777,215, or 2
24
-1). The output is fed into the A/D timing circuit and can be
selected to trigger A/D conversions when AINTE is 1 and CLKSEL is 0 in Base + 13 (bit 1). Using
the control registers at Page 0 : Base + 13 and Base + 27, the counter can be loaded, cleared,
enabled, and disabled, the optional gate can be enabled and disabled, and the counter value can
be latched for reading.
14.2 Counter 1 – Counting/Totalizing Functions
The second counter, Counter 1, is similar to Counter 0 except it is a 16-bit counter. It also has an
internal clock input, as well as an external input (“EXTTRIG”), an external gate (“GATE 1”), and
an output (“TOUT1”). The gate and output signals are present on the I/O header only when
DIOCTR=0. The input may come from either the external trigger signal or the on-board clock
generator. When the on-board clock generator is used, the clock frequency is either 10MHz or
100 KHz as determined by control bit CKFRQ1, located at Page 0: Base + 12, bit 1.
The output (“TOUT1”) is a positive-going pulse that appears on pin 38 of I/O header J8 (when
DIOCTR1 = 1). The output pulse occurs when the counter reaches zero. When the counter
reaches zero it will reload and start over on the next clock pulse. The output stays high the entire
time the counter is at zero, i.e. from the input pulse that causes the counter to reach zero until the
input pulse that causes the counter to reload.
When CLKSRC1=1 (external source), then Counter 1 operates as follows: It counts positive
edges of the signal on pin 41 (“EXTTRIG”) on the I/O header. The counter can either be free
running or gated, as determined by the Gate Enable control bit, “GTEN” (Page 0 : Base +27, bit
4).
The gate signal is provided on pin 37 when DIOCTR1 = 1 (enabling counter functions on I/O
header) and GTEN = 1 (enabling gating for this counter). If the gate signal is high then the
counter will count, and if it is low the counter will hold its value and ignore input pulses. This pin
can have a pull-up so the counter can operate without any external gate signal (See section on
DIO pull-up’s on page 97).
When DIOCTR1=0, Counter 1 operates as follows: It takes its input from the on-board clock
generator based on the value of the CKFRQ1 bit located at Page 0: Base + 12. There is no gating
and the counter runs continuously.