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Chapter 3 Hardware Installation
22
Chapter 3
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
CM960-B
Carrier Board
Description
ȟ
ȟ
ȟ
ȟ
USB Signals Descriptions
US
C7
USB_SSRX1-
C6
US
D10
AC Coupling capacitor
USB_SSTX2-
D9
AC Coupling capacitor
US
C10
USB_SSRX2-
C9
US
D13
AC Coupling capacitor
USB_SSTX3-
D12
AC Coupling capacitor
US
C13
USB_SSRX3-
C12
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
CM960-B
Carrier Board
Description
A71
LVDS_A0-
A72
A73
LVDS_A1-
A74
A75
LVDS_A2-
A76
A78
LVDS_A3-
A79
LV
A81
LVDS_A_CK-
A82
B71
LVDS_B0-
B72
B73
LVDS_B1-
B74
B75
LVDS_B2-
B76
B77
LVDS_B3-
B78
LV
B81
LVDS_B_CK-
B82
LVDS_VDD_EN
A77
O CMOS
3.3V / 3.3V
Connect to enable control of LVDS panel power
circuit
LVDS panel power enable
LVDS_BKLT_EN
B79
O CMOS
3.3V / 3.3V
Connect to enable control of LVDS panel backlight
power circuit.
LVDS panel backlight enable
LVDS_BKLT_CTRL
B83
O CMOS
3.3V / 3.3V
Connect to brightness control of LVDS panel
backlight power circuit.
LVDS panel backlight brightness control
LVDS_I2C_CK
A83
I/O OD CMOS 3.3V / 3.3V
NA
NA
I2C clock output for LVDS display use
LVDS_I2C_DAT
A84
I/O OD CMOS 3.3V / 3.3V
NA
NA
I2C data line for LVDS display use
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ȟ
ȟ
ȟ
LVDS
AC coupled on Module
Additional transmit signal differential pairs for the SuperSpeed USB data path.
I PCIE
AC coupled off Module
Additional receive signal differential pairs for the SuperSpeed USB data path.
O PCIE
AC coupled on Module
Additional transmit signal differential pairs for the SuperSpeed USB data path.
I PCIE
AC coupled off Module
Additional receive signal differential pairs for the SuperSpeed USB data path.
Connect to LVDS connector
LVDS Signals Descriptions
O LVDS
LVDS
Connect to LVDS connector
LVDS Channel A differential pairs
Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-, LVDS_B[0:3]+/-. LV/-,
LV/-) shall have 100
ƻ
terminations across the pairs at the destination. These
terminations may be on the Carrier Board if the Carrier Board implements a LVDS deserializer
on-board
O LVDS
Connect to LVDS connector
O LVDS
LVDS
Connect to LVDS connector
LVDS
LVDS
Connect to LVDS connector
O LVDS
LVDS
O LVDS
LVDS
LVDS Channel B differential clock
O LVDS
O LVDS
LVDS
Connect to LVDS connector
O LVDS
LVDS
Connect to LVDS connector
Connect to LVDS connector
LVDS Channel A differential clock
O LVDS
LVDS
Connect to LVDS connector
O LVDS
Connect to LVDS connector
Connect 90
ಳ
@100MHz Common Choke in series
and ESD suppressors to GND to USB connector
Connect 90
ಳ
@100MHz Common Choke in series
and ESD suppressors to GND to USB connector
Connect 90
ಳ
@100MHz Common Choke in series
and ESD suppressors to GND to USB connector
Connect 90
ಳ
@100MHz Common Choke in series
and ESD suppressors to GND to USB connector
Connect 90
ಳ
@100MHz Common Choke in series
and ESD suppressors to GND to USB connector
LVDS Channel B differential pairs
Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-, LVDS_B[0:3]+/-. LV/-,
LV/-) shall have 100
ƻ
terminations across the pairs at the destination. These
terminations may be on the Carrier Board if the Carrier Board implements a LVDS deserializer
on-board
I PCIE
AC coupled off Module
Additional receive signal differential pairs for the SuperSpeed USB data path.
O PCIE
Содержание CM960-B
Страница 1: ...www dfi com Chapter 1 Introduction 1 CM960 B COM Express Basic Module User s Manual A32100420...
Страница 62: ...www dfi com Chapter 5 Supported Software 62 Chapter 5 WatchDog DIO Backlight...
Страница 76: ...www dfi com 76 Appendix E Appendix E BIOS Status Code PEI Beep Codes DXE Status Codes...
Страница 77: ...www dfi com 77 Appendix E Appendix E BIOS Status Code...