DFI 686IPK, Руководство пользователя

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49
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
Auto Configuration
DRAM RAS# Precharge Time
MA Additional Wait State
RAS# To CAS# Delay
DRAM Read Burst (B/E/F)
DRAM Write Burst (B/E/F)
ISA Bus Clock
DRAM Fast Leadoff
DRAM Refresh Queue
DRAM RAS Only Refresh
DRAM ECC/Parity Select
Fast DRAM Refresh
Read-Around-Write
PCI Burst Write Combine
PCI-To-DRAM Pipeline
CPU-To-PCI Write Post
CPU-To-PCI IDE Posting
: Enabled
: 4
: Disabled
: Enabled
: x2/3/4
: x3/3/3
: PCICLK/4
: Disabled
: Enabled
: Disabled
: Disabled
: Disabled
: Enabled
: Disabled
: Enabled
: Enabled
: Disabled
System BIOS Cacheable
Video BIOS Cacheable
VGA Write Combining
8 Bit I/O Recovery Time
16 Bit I/O Recovery Time
Memory Hole At 15M-16M
Passive Release
Delayed Transaction : Disabled
: Enabled
: Disabled
: 4
: 2
: Disabled
: Enabled
: Disabled
ESC
F1
F5
F6
F7 : Quit
: Help
: Old Values
: Load BIOS Defaults
: Load Setup Defaults
PU/PD/+/-
(Shift) F2
: Select Item
: Modify
: Color
↑ ↓ → ←
Auto Configuration
Enabled
Disabled
The system will set the “DRAM RAS# Precharge Time” to
the “ISA Bus Clock” categories automatically.
This allows you to set the “DRAM RAS# Precharge Time” to
the “ISA Bus Clock” categories manually.
DRAM ECC/Parity Select
Enables the memory parity check. If the system DRAM has no
parity bit, the system will display “RAM parity error”.
The system will ignore the memory parity check even if the
DRAM has no parity bit. The system will not display “RAM
parity error”.
Enables the ECC (Error Correction Code) function.
Parity
Disabled
ECC
ISA Bus Clock
The PCI Bus Clock is 33MHz and the ISA bus clock is
8.25MHz.
The PCI Bus Clock is 33MHz and the ISA bus clock is
11MHz.
PCICLK/4
PCICLK/3
Warning:
We recommend that you set the ISA Bus Clock category to “PCICLK/4”. Compatibility
problems with some ISA cards may occur if the ISA Bus Clock is set at “PCICLK/3”.