74
S-301
SM8701BM (IC113: 1U-3692)
SN74LV273APW (IC106, 107: 1U-3692)
SN74AHCT273PW (IC105: 1U-3692)
SN74LV573APW (IC903, 904: 1U-3694)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
MLEN/R2
P/S
V
DD
GND
XTO
XTI
GNDP
V
DD
P
V
DD
3
MO
MCK/R1
MDT/R0
RSTN
SO3
V
DD
O
GNDO
SO2
SO4
SO1
MON
14
13
12
11
Control signal input.
1
MLEN/R2
Ip
1
In serial mode: latch enable signal
In parallel mode: sampling rate select signal
2
P/S
Ip
1
Mode select signal.
LOW: serial mode, HIGH: parallel mode
3
V
DD
5V supply (Digital block)
4
GND
Ground (Digital block)
5
XTO
O
Reference signal crystal oscillator element connection
6
XTI
I
Reference signal crystal oscillator element connection
or external clock input
7
GNDP
Ground (PLL block)
8
V
DD
P
5V supply (PLL block)
9
V
DD
3
3.3V supply (output buffer)
10
MO
O
27 MHz fixed-frequency output
11
MON
O
27 MHz fixed-frequency output (inverted)
12
SO1
O
33.8688 MHz fixed-frequency output
13
SO4
O
768fs output
14
SO2
O
256fs output
15
GNDO
Ground (output buffer)
16
V
DD
O
3.3V supply (output buffer)
17
SO3
O
384fs output
18
RSTN
Ip
2
LOW-level reset input
Control signal input.
19
MDT/R0
Ip
1
In serial mode: control data input signal
In parallel mode: sampling frequency select signal
Control signal input.
20
MCK/R1
Ip
1
In serial mode: clock signal
In parallel mode: sampling frequency select signal
Pin Name
Function
Pin No.
I/O
SM8701BM Terminal Function
Note:
1. Schmitt trigger input with pull-down resistor
2. Schmitt trigger input with pull-up resistor
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
CLR
1Q
1D
2D
2Q
3Q
3D
4D
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
logic diagram (positive logic)
CLK
1D
1Q
2D
2Q
3D
3Q
4D
4Q
5D
5Q
6D
6Q
7D
7Q
8D
8Q
CLR
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
3
4
7
8
13
14
17
18
2
5
6
9
12
15
16
19
11
1
6
7
8
10
9
15
14
13
12
11
D4
D5
D6
D7
GND
Q4
Q5
Q6
Q7
LE
D
Q
L
D
Q
L
D
Q
L
D
Q
L
D
Q
L
D
Q
L
D
Q
L
D
Q
L
D0
D1
D2
D3
D4
D5
D6
D7
L
E
OE
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
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2
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8
0
5
1
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1
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7
3
Q
Q
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