18
S-301
TSD0
33
O
Audio transmit serial data port 0.
SEL_PLL0
I
Refer to the description and matrix for SEL_PLL2 pin 32.
TSD1
36
O
Audio transmit serial data port 1.
SEL_PLL1
I
Refer to the description and matrix for SEL_PLL2 pin 32.
TSD2
37
O
Audio transmit serial data output 2.
TSD3
38
O
Audio transmit serial data output 3.
NC
48
—
No connect pins. Leave open.
MCLK
39
I/O
Audio master clock for audio DAC.
TBCK
40
O
Audio transmit bit clock.
SEL_PLL3
41
I
Clock source select. Strapped to VCC or ground via 4.7-k
Ω
resistor; read only
during reset.
SPDIF_OUT
O
S/PDIF output.
SPDIF_IN
42
I
S/PDIF input.
RSD
45
I
Audio receive serial data.
RWS
46
I
Audio receive frame sync.
RBCK
47
I
Audio receive bit clock.
XIN
49
I
27-MHz crystal input.
XOUT
50
O
27-MHz crystal output.
AVEE
51
P
Analog power for PLL.
AVSS
52
G
Analog ground for PLL.
DMA[11:0]
53:58, 61:66
O
DRAM address bus.
DCAS#
69
O
DRAM column address strobe.
DOE#
O
DRAM output enable (active-low).
O
DRAM clock enable.
O
DRAM write enable (active-low).
O
DRAM row address strobe (active-low).
O
DRAM bank select 0.
O
DRAM bank select 1.
I/O
DRAM data bus.
O
DRAM chip select (active-low).
DQM
101
O
Data input/output mask.
p
(
)
Name
Pin Numbers
I/O
Definition
SEL_PLL3
Clock Source
0
Crystal oscillator
1
DCLK input
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