19
S-301
DSCK
102
O
Output clock to DRAM.
DCLK
105
I
Clock input to PLL.
YUV0
106
O
YUV pixel 2 output data.
CAMIN2
I
Camera YUV 2.
UDAC
O
Video DAC output.
F: CVBS/chroma signal for simultaneous mode.
Y: Luma component for YUV and Y/C processing.
C: Chrominance signal for Y/C processing.
U: Chrominance component signal for YUV mode.
V: Chrominance component signal for YUV mode.
YUV1
O
YUV pixel 1 output data.
I
Internal voltage reference to video DAC. Bypass to ground with 0.1-
µ
F capacitor.
O
YUV pixel 2 output data.
O
Video DAC output. Refer to description and matrix for UDAC pin 106.
O
YUV pixel 3 output data.
I
Compensation input. Bypass to ADVEE with 0.1-
µ
F capacitor.
O
YUV pixel 4 output data.
I
DAC current adjustment resistor input.
ADVEE
111
P
Analog power for video DAC.
p
(
)
Name
Pin Numbers
I/O
Definition
Pin
115
114
113
108
106
Value
F DAC
V DAC
Y DAC
C DAC
U DAC
0
CVBS/Chroma
CVBS1
Y
C
N/A
1
CVBS/Chroma
CVBS1
Y
C
CVBS2
2
CVBS/Chroma
N/A
Y
C
N/A
3
CVBS/Chroma
CVBS1
N/A
N/A
CVBS2
4
CVBS/Chroma
CVBS1
N/A
N/A
N/A
5
CVBS/Chroma
CVBS1
Y
Pb
Pr
6
CVBS/Chroma
N/A
Y
Pb
Pr
7
N/A
SYNC
G
B
R
8
CVBS/Chroma
Chroma
Y
Pb
Pr
9
CVBS
CVBS1
G
B
R
10
CVBS
CVBS1
G
R
B
11
N/A
SYNC
G
R
B
12
CVBS/Chroma
N/A
Y
Pr
Pb
13
CVBS/Chroma
CVBS1
Y
Pr
Pb
14
Chroma
Y
G
R
B
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