31
S-301
31 SYSCK
O
D
Clock
Clock Monitor output.
32 DV
DD
18
P
V
DD
& GND
Digital 1.8V Power. (Internal logic system power)
33 XI
I
D
Clock
Crystal oscillation input.
34 XO
O
D
Clock
Crystal oscillation output.
35 DV
SS
P
V
DD
& GND
Digital Ground.
36 VDT7
O
D
VSTEM A/V
MPEG data output 7.
37 VTD6
O
D
VSTEM A/V
MPEG data output 6.
38 DV
SS
P
V
DD
& GND
Digital Ground.
39 VDT5
O
D
VSTEM A/V
MPEG data output 5.
40 VDT4
O
D
VSTEM A/V
MPEG data output 4.
41 VDT3
O
D
VSTEM A/V
MPEG data output 3.
42 VDT2
O
D
VSTEM A/V
MPEG data output 2.
43 VDT1
O
D
VSTEM A/V
MPEG data output 1.
44 VDT0
O
D
VSTEM A/V
MPEG data output 0.
45 HDRQ
I
D
VSTEM A/V
MPEG data Request input.
*
46 XHAC
O
D
VSTEM A/V
Data Valid output.
47 VEFG
O
D
VSTEM A/V
ECC Error-sector Flag output. (L: error sector)
48 XSHD
O
D
VSTEM A/V
DVD Sector Head Flag output.
49 DCK
O
D
VSTEM A/V
Data Strobe output.
50 DRVIRQ
O
D
VSTEM Command Interrupt Request output for Host. (L: interruption is demanded)
51 DRVRST
I
D
VSTEM Command Drive H/W Reset input. (L: reset)
*
*
52 DV
DD
18
P
V
DD
& GND
Digital 1.8V power for Internal logic system.
53 DV
DD
33
P
V
DD
& GND
Digital 3.3V Power for I/O.
54 DRVTX
O
D
VSTEM Command Transmitting serial data output to Host.
55 DRVRX
I
D
VSTEM Command Reception serial data input from Host.
56 DRVCLK
I
D
VSTEM Command Clock input from Host.
*
57 DRVRDY
O
D
VSTEM Command Drive Ready signal output. (L: ready)
58 C2PO
O
D
Audio I/F
CD-DSP C2 Pointer output.
59 DADT
O
D
Audio I/F
Audio serial data output.
60 DOTX
O
D
Audio I/F
Digital audio output.
61 LRCK
O
D
Audio I/F
L/R Clock output.
62 BCK
O
D
Audio I/F
Audio Bit Clock output.
63 EXVCO
I
D
TEST/Monitor
External Channel clock input.
64 EXPLDT
I
D
TEST/Monitor
External RF data input. (Logic level)
65 CSL
O
D
ASP I/F
SIO for RF signal processing LSI control. Latch signal output.
66 SI
I
D
ASP I/F
SIO for RF signal processing LSI control. Serial data input.
67 SO
O
D
ASP I/F
SIO for RF signal processing LSI control. Serial data output.
68 SCLKH
O
D
ASP I/F
SIO for RF signal processing LSI control. Serial clock output.
69 RFOKGH
I
D
ASP I/F
RF O.K. Signal input.
*
70 HFD
I
D
ASP I/F
RF lack Signal input.
*
ASP I/F
Mirror detected signal input.(H: Mirror detected)
*
ASP I/F
Track cross signal input. (Logic level input)
*
V
DD
& GND
Analog Ground.
Data PLL
Track Cross signal input. (Analog level input)
Data PLL
RF signal input.
Data PLL
Asymmetry Charge-pump output 0.
Data PLL
Asymmetry Charge-pump output 1
Data PLL
Reference current setting terminal for Asymmetry Circuit.
V
DD
& GND
Analog 3.3V Power.
Data PLL
Reference current setting terminal for Jitter Monitor
Data PLL
Jitter Monitor output.
82 CHG
I
A
Data PLL
Reference current setting terminal for data PLL.
83 VFBC
I
A
Data PLL
VCO offset frequency setting terminal for data PLL.
84 AV
DD
18
P
V
DD
& GND
Analog 1.8V Power.
85 VCOI
I
A
Data PLL
VCO Control voltage input terminal for data PLL.
86 LPF1
O
A
Data PLL
VCO Loop-filter connection terminal 1 for data PLL.
87 LPF2
O
A
Data PLL
VCO Loop-filter connection terminal 2 for data PLL
88 RC
I
A
Data PLL
VCO gain setting terminal for data PLL.
89 AV
SS
P
V
DD
& GND
Analog Ground.
90 AV
SS
P
V
DD
& GND
Analog Ground.
91 AD0
I
A
ADC
AD0 Input.
No. Terminal Name I/O
A/D
Classification
Function
PU PD SMT
www. xiaoyu163. com
QQ 376315150
9
9
2
8
9
4
2
9
8
TEL 13942296513
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299