Denon DVD-310, Руководство по обслуживанию

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15
15
DVD-310
T431616A-8S(ME:U5)
PIN PIN NAME DESCRIPTION
CLK System Clock
Active on the positive going edge to sample all input.
CKE Clock Enable
Disables or enables device operation by masking or enabling all input
except CLK,CKE and L(U)DQM
CS Chip Select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
BA Bank Select Address
A0 ~ A10/AP
DQ0 ~ DQ15
Address
Selects bank to activated during row address latch time.
Select bank for read/write during column address latch time.
Row/column aaddresses are multiplexed on the same pins.
Row address : RA0 ~ RA10,column address : CA0 ~ CA7
RAS
CAS
WE
Row Address Strobe
Column Address Strobe
Write Enable
Latches row addresses on the positive going edge of the CLK
with RAS low.
Enables row access & precharge.
L(U)DQM Data Input/Output Mask
Data Input/Output
Latches column addresses on the positive going edge of the CLK
with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
V
DD
/V
SS
Power Supply/Ground
Data inputs/outputs are multiplexed on the same pins.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
V
DDQ
/V
SSQ
Data Output Power/Ground
N.C/RFU
No Connection/Reserved
for Future Use
This pin is recommended to be left No Connection on the device.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
Powe and ground for the input buffers and the core logic.
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
DQ10
V
SSQ
DQ9
V
DDQ
DQ8
N . C / RFU
UDQM
CLK
CKE
N . C
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
DD
DQ0
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
V
DD
PIN DESCRIPTION
V
DDQ