Denon DN-X600, Руководство по обслуживанию

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Pin No BGA Location Pin name I/O Pol Reg Function
131 J3 ADC_MCLK O Audio master clock for INPUT UNIT
132 J4 SHDB1.. IO 16bits data bus (CPU)
133 J5 V3FPG VCCO
134 J6 NC NC
135 J7 SHRD I N Read enable (CPU)
136 J8 DGND DGND
137 J9 V1FPG VCCINT
138 J10 SRCD_3 I Digital Audio data (AK4125)
139 J11 SRCD_4 I Digital Audio data (AK4125)
140 J12 FEMA12 I 13bits address bus (DSP)
141 J13 FEMA11 I 13bits address bus (DSP)
142 J14 OUTD_4 O Selected Audio data
143 J15 V3FPG VCCO
144 J16 OUTD_1 O Selected Audio data
145 K1 NC NC
146 K2 DGND DGND
147 K3 AHCLK O Audio master clock for DSP
148 K4 SHDB2.. IO 16bits data bus (CPU)
149 K5 LRCKO_1. I LR clock form DIR9001
150 K6 LRCKO_2. I LR clock form DIR9001
151 K7 DGND DGND
152 K8 V1FPG VCCINT
153 K9 DGND DGND
154 K10 V1FPG VCCINT
155 K11 DSP_CE I N Chip enable (DSP)
156 K12 DSP_OE I N Out enable (DSP)
157 K13 FEMA10 I 13bits address bus (DSP)
158 K14 INPUT_LRCK O LR clock for INPUT UNIT
159 K15 OUTPUT_LRCK O LR clock for OUTPUT UNIT
160 K16 INPUT_BCK O Bit clock for INPUT UNIT
161 L1 SHDB11.. IO 16bits data bus (CPU)
162 L2 SHDB8.. IO 16bits data bus (CPU)
163 L3 SHDB5.. IO 16bits data bus (CPU)
164 L4 SHDB3.. IO 16bits data bus (CPU)
165 L5 LRCKO_3. I LR clock form DIR9001
166 L6 LRCKO_4. I LR clock form DIR9001
167 L7 UOUT_1 I SPDIF user bit form DIR9001
168 L8 UOUT_2 I SPDIF user bit form DIR9001
169 L9 UOUT_3 I SPDIF user bit form DIR9001
170 L10 UOUT_4 I SPDIF user bit form DIR9001
171 L11 DGND DGND
172 L12 V3FPG VCCAUX
173 L13 FEMA9 I 13bits address bus (DSP)
174 L14 FEMA6 I 13bits address bus (DSP)
175 L15 DGND DGND
176 L16 FEMA2 I 13bits address bus (DSP)
177 M1 SHDB12.. IO 16bits data bus (CPU)
178 M2 V3FPG VCCO
179 M3 SHDB6.. IO 16bits data bus (CPU)
180 M4 SHDB4.. IO 16bits data bus (CPU)
181 M5 DGND DGND
182 M6 V3FPG VCCAUX