Denon DN-X600, Руководство по обслуживанию

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R5S72630P200FP Block Diagram
R5S72630P200FP Terminal Function
Pin No Pin name I/O Pol Function
1 PC10/RASU I MONO H=Stereo(default), L=Mono
2 /CASL O N SDRAM(IC107) / Column Adress Strobe
3 /RASL O N SDRAM(IC107) / Row Adress Storbe
4 VCC VCC
5 DQMUU O SDRAM(IC107) / Input/Output Mask
6 VSS DGND
7 PVSS DGND
8 DQMUL O SDRAM(IC107) / Input/Output Mask
9 PVCC PVCC
10 DQMLU O SDRAM(IC107) / Input/Output Mask
11 /CS0 O N FLASH(IC103) / Chip Enable
12 /RD O N FLASH(IC103) /Output Enable, ADSP / UHPI Select Signals
13 DQMLL, /WE0 O SDRAM(IC107) / Input/Output Mask 1, ADSP UHPI Select Signals
14 PC3/CS3 O N SDRAM(IC107) / Chip Select
15 PC2/CS2 O N FPGA / Panel scan signal
16 VCC VCC
17 PC0/A0/CS7 O N FPGA / Chip Select
18 VSS DGND
19 PVSS DGND
SH-2A
CPU core
Pin function
controller
(PFC)
I/O ports
Clock pulse
g enerator
(CPG)
Interrupt
controller
(INTC)
Compare
match
timer
(CMT)
Multi-function
timer pulse
unit 2
(MTU2)
Watchdo g
timer
(WDT)
Realtime
clock
(RTC)
Internal CPU bus
(IC bus)
Internal DMA bus
(ID bus)
Peripheral bus (P clock)
Port Port Port Port Port Port
General I/O EXTAL input
XTAL output
CKIO I/O
Clock mode input
RTC_X1 input
RTC_X2 output
RES
input
MRES
input
MMI input
IRQ input
PINT input
IRQOUT
output
Timer pulse I/O
WDTOVF
output
DREQ input
DACK output
TEND output
Cache
controller
Instruction
cache memory
8 Kbytes
Operand
cache memory
8 Kbytes
On-chip RAM
(hi g h-speed)
64 Kbytes
User
debu gg in g
interface
(H-UDI)
Port
JTAG I/O
Power-down
mode
control
On-chip RAM
(retention)
16 Kbytes
SD host
interface
(SDHI)
Port
SD card I/F I/O
Samplin g
rate
converter
(SRC)
AND/NAND
flash memory
controller
(FLCTL)
Port
Flash memory
I/F I/O
D/A converter
(DAC)
Port
Analo g output
A/D converter
(ADC)
Port
Analo g input
ADTRG
input
IEBusTM
controller
(IEB)
Port
IEBus input
Controller
area
network
(RCAN-TL1)
Port
CAN bus I/O
Serial
sound
interface
(SSI)
Port
Serial I/O
Audio clock input
Serial
communication
interface with FIFO
(SCIF)
I
2
C bus
interface 3
(IIC3)
Port Port Port
Serial I/O Serial I/O
Internal LCD bus
(IL bus)
LCD I/F I/O
CD-ROM
decoder
(ROM-DEC)
USB2.0 host/
function module
(USB)
Port
USB bus I/O
USB clock input
Bus state
controller
(BSC)
Port
External bus I/O
External bus width
mode input
User break
controller
(UBC)
UBCTRG
output
LCD
controller
(LCDC)
Peripheral
bus controller
Direct memory
access
controller
(DMAC)
Floatin g -point
unit (FPU)
Internal bus
(I bus)
(B clock)
Po
rt
Po
rt
Po
rt
CPU bus
(C bus)
(I clock)
CPU memory access bus (M bus)
CPU instruction fetch bus (F bus)
Synchronous
serial commnication
unit
(SSU)
I
2
C bus I/O