MVBX2-X User’s Manual
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the CPU. When disabled, a write buffer is not used and the CPU read cycle will not be
completed until the PCI bus signals that it is ready to receive the data.
PCI Dynamic Bursting
When Enabled, every write transaction goes to the write buffer. Burstable trans-actions
then burst on the PCI bus and nonburstable transactions don’t.
PCI Master 0 WS Write
When Enabled
,
writes to the PCI bus are executed with zero wait states.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions
cycles. Select Enabled to support compliance with PCI specification version 2.1.
PCI#2 Access #1 Retry
This item allows you Enable or Disable the PCI#2 Access #1 Retry.
AGP Master 1 WS Write
This implements a single delay when writing to the AGP Bus. By default, two-wait states
are used by the system, allowing for greater stability.
AGP Master 1 WS Read
This implements a single delay when reading to the AGP Bus. By default, two-wait states
are used by the system, allowing for greater stability.
Assign IRQ For Assign IRQ For VGA
Name the interrupt request (IRQ) line assigned to the /VGA on your system. Activity of the
selected IRQ always awakens the system.
