Datex-Ohmeda CAPNOMAC ULTIMA, Руководство по обслуживанию

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CAPNOMAC ULTIMA
TM
SERVICE MANUAL
5-26
5.6 CPU board (Rev. 06 and up)
Block diagram and schematic diagram part 1
Figure 5.14
Parts layout and schematic diagram part 2 Figure 5.15
Jumper configuration and schematic diagram part 3 Figure 5.16
Principle of operation
The High Speed CPU board contains 16 MHz oscillator (previously
11.059 MHz), 80C32 CPU, standard EPROM and SRAM, and
several analog and digital I/O functions. See the CPU board block
diagram.
The CPU (D5) uses the CPU board internal bus to access most of
the peripheral circuits; the on-chip peripheral ports are directly
used for analog multiplexers (MUX) and serial channel 0 (ASCII
computer output). The computer output is explained in Appendix
A.
There are jumpers to select memory chips. They are 2M bit
program EPROM (Dl), 128 x 8 kbit low current CMOS SRAM
(D6) powered by the data retention voltage, and battery back-up 8
kbit SRAM (D4) for permanent calibration value memory. See the
jumper configuration.
Analog input signals are read through the multiplexer (A3) to the
A/D-converter A2.
Control signals of MUX are in port 1 on the microprocessor as
follows:
P1 pins 3-5
pin 6
pin 7
pin 8
ADC 4
ADC6
DAC 2
DAC 6
DAC 5
DAC 7
MUX A0-A2 (both)
MUX enable (both)
MUX 0 Write (ADC)
MUX 1 Write (DAC)
Ired signals
Red signals
SpO
2
Ired pleth
Loudspeaker volume
Loudspeaker pitch
January 15th, 1997/6