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Application Note

(AN241)

PCI-FRM01 Register Level Application Guide



2005 DAQ system, all rights reserved.

http://www.daqsystem.com

4. Memory Address Usage

SDR SRAM for future enhancements can be used.

SDR SDRAM 64M Byte

0h - 4000000h

Description

Memory Address

Space

Undefined

Model

Reserved

Comment

UART (0x60)

LVDS (0xC0)

DIO (0xD0)

Interrupt (0xB0)

Reserved

FFh

00h

Reserved
64M Byte

000000h

3FFFFFFh

Memory region

I/O region

Reserved

Reserved

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Содержание PCI-FRM01

Страница 1: ...their own property Information furnished by DAQ system is believed to be accurate and reliable However no responsibility is assumed by DAQ system for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or copyrights of DAQ system The information in this document is subject to ...

Страница 2: ...tem all rights reserved http www daqsystem com Contents 1 PCI BUS Address Space 2 PCI FRM01 Functional Block Diagram 3 I O Address Usage 4 Memory Address Usage 5 UART Usage 6 Interrupt Controller Usage 7 LVDS Camera Link Interface Usage 8 DIO Digital Input Output Usage References ...

Страница 3: ...ry and I O area In order to support Plug Play in case of PCI bus that has a special configuration It can make the resource and device state control register etc Memory Area I O Area Configuration Area 4G 64K 64DWORD The PCI FRM01 use a memory and I O that have been assigned to system for operation the contents are as follows that they required Address Area Requirements Remark Memory Maximum 64MByt...

Страница 4: ...an not be used in the most application because of only using resources for the system boot time PCI Target PCI BUS Local Bus Address Data Mem I O Reserved 0x00 0x5F Reserved 0x70 0xAF UART 0x60 Camera Link LVDS 0xC0 Interrupt controller DIO 0xD0 Ext Address Data Control Local BUS Interrupt Controller 0xb0 INT sources in Chip IO Decoder MEM Decoder To each IO Module PCI FRM01 INTERNAL BLOCK FPGA DP...

Страница 5: ...address indicates the base address of the peripheral device All I O registers are 32 bit input output processing Reserved area for future use 00h 5Fh Description I O Address Offset Base Reserved Function 60h 70h AFh Universal asynchronous receiver transmitter RS232C Reserved area for future use UART Reserved Frame grabber LVDS interface C0h D0h E0h FFh Photo coupler isolated Digital input Output R...

Страница 6: ...qsystem com 4 Memory Address Usage SDR SRAM for future enhancements can be used SDR SDRAM 64M Byte 0h 4000000h Description Memory Address Space Undefined Model Reserved Comment UART 0x60 LVDS 0xC0 DIO 0xD0 Interrupt 0xB0 Reserved FFh 00h Reserved 64M Byte 000000h 3FFFFFFh Memory region I O region Reserved Reserved ...

Страница 7: ...atus Register Data Buffer Register Baud Control Status 1 Data Buffer 2 Baud rate generator 40Mhz Initial Value x 82 3 Control 0 1 8 31 Reserved UART Control Register Bit Position Usage 2 3 4 5 6 7 RE TE Bit Name Description Default Value 0 RE Receiver Interrupt Enable 0 1 TE Transmitter Interrupt Enable 0 31 2 Reserved For future use All 0 4 STATUS 8 31 Reserved UART STATUS Register Bit Position U...

Страница 8: ...Note AN241 PCI FRM01 Register Level Application Guide 2005 DAQ system all rights reserved http www daqsystem com 3 FE Frame Error 0 4 TI Transmit Interrupt 0 5 TB Transmit Busy 0 31 2 Reserved For future use All 0 ...

Страница 9: ...mode have to set up through the control register To all setup most significant bit MSB is set to high 1 and write to the control register If the MSB is 0 it will be command of PORTC For more information refer 82C55 manual When the first time power is applied all ports will be the input and operation modes will be 0 1 INT_STA Interrupt Status Indicates the current interrupt device that requires To ...

Страница 10: ...sing Edge Trigger 3 INT_EN Each interrupt source is to enable the interrupt 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 G Enable E0 31 Reserved INTERRUPT Enable Register Bit Position meaning E14 16 If each bit is 1 the device interrupt for corresponding bit will be enabled The bit 15 is Global Interrupt Enable This bit is set to 1 to enable all interrupts 4 INT_SRC INT_STA appear on the register the int...

Страница 11: ...ter LVDS_DATA Register LVDS_CMD LVDS_CNT LVDS_STA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Data LVDS Data Register Bit Position meaning D31 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 D0 0 1 2 3 4 31 Reserved LVDS Command Register Bit Position meaning 5 D I E R S Bit Name Description Default Value 0 Enable Used for simulation 0 1 Reset 0 2 Data Enable 0 3 Interrupt Enable 0 4 Start 0 15 0 1 2 3 4...

Страница 12: ...1 12 13 14 PC Address LVDS Address LVDS Status Register Bit Position meaning A10 V 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 15 A0 Bit Name Description Default Value 10 0 PC address Dual port ram address 11 Done 0 12 Data Ready 0 13 Lvalid 0 14 Fvalid 0 15 Interrupt 0 27 16 LVDS address Dual port ram address 28 Reserved 29 Data ready 0 30 Hsync 0 31 Vsync 0 ...

Страница 13: ... 6Bit Photo coupler input 10Bit LVDS input Port For future use For future use Out Port Register In Port Reserved Reserved 0 1 Used 4 31 Reserved DIO Out Port Register Bit Position Usage 2 3 4 5 6 7 Bits 3 0 are the Photo coupler isolated Digital outputs bits 7 4 are the LVDS outputs Please refer to the manual for the circuit configuration 0 Used 16 31 Reserved DIO In Port Register Bit Position Usa...

Страница 14: ...qsystem com References 1 Specifications of the Camera Link Interface Standard for Digital Cameras and Frame Grabbers PULNix America Inc 2 Channel Link Design Guide National Semiconductor 3 PCI EK01 A B User s Manual DAQ system 4 DS90CR285 286 chip manual National Semiconductor 5 PCI FRM01 User s manual DAQ system ...

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