Application Note
(AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved.
http://www.daqsystem.com
2. PCI-FRM01 Functional Block Diagram
The address area assigned by the system in the PCI-FRM01 division is shown in the figure below.
Most peripheral control and status register is in the I/O area, only SDR SRAM is in the memory area.
The configuration area can not be used in the most application because of only using resources for the
system boot time.
PCI Target
PCI BUS
Local Bus
Address
Data(Mem,I/O)
Reserved
(0x00
?
0x5F)
Reserved
(0x70
?
0xAF)
UART
(0x60)
Camera Link(LVDS)
(0xC0)
Interrupt controller
DIO
(0xD0)
Ext. Address, Data, Control
Local BUS
Interrupt
Controller
(0xb0)
INT sources in Chip
IO Decoder
MEM Decoder
To each IO
Module
PCI-FRM01 INTERNAL BLOCK - FPGA
DPRAM
From Ext.
CLOCK syn.
MEM Decoder
BUS Mux
Reserved
(0xE0
?
0xFF)
PCI-FRM01 of the figure shows the function block, which features the dotted area is reserved for
future feature additions.
