Application Note
(AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved.
http://www.daqsystem.com
11
Interrupt
Reserved
‘
0
’
12
LVDS
Reserved
‘
0
’
13
Reserved
‘
0
’
14
Reserved
‘
0
’
15
Global
When any of the above interrupt sources need
the processing, it will be changed '1'.
‘
0
’
31-16
Reserved
For future use
All
‘
0
’
For more information, refer AD5324 manual
.
(2) INT_SEL
Select the Level Trigger and Edge Trigger of Interrup Input.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Status Clear
C0
31
Reserved
INTERRUPT
Clear Register Bit Position & meaning
C14
16 15
R
If it is
“0”, it is a Level Trigger. If it is “1”, it is a Rising Edge Trigger.
(3) INT_EN
Each interrupt source is to enable the interrupt.
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
G
Enable
E0
31
Reserved
INTERRUPT
Enable Register Bit Position & meaning
E14
16
If each bit is
‘1’, the device interrupt for corresponding bit will be enabled.
The bit 15 is Global Interrupt Enable. This bit is set to '1' to enable all interrupts.
(4) INT_SRC
INT_STA appear on the register, the interrupt request output of the device is latched at the rising
edge of the signal. Thus, it is not Level Trigger, it is an indication of Edge Triggere.
So, it can be cleared and requested the interrupt. On the other hand, in the INT_SRN, it represents
current output signal state of the current device.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Interrupt Source
S0
31
Reserved
INTERRUPT
Source Indicator Bit Position & meaning
S14
15
