PCIe-FRM24 Users Manual (Rev 1.3)
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http://www.daqsystem.com
2. PCIe-FRM24 Functions
2.1 Block Diagram
As shown in the following figure, main control of the board is performed in FPGA Core Logic.
Primary functions are receiving the image frame data, camera control signal and external Line
Trigger I/O.
You can control these functions using API provided by DAQ system through PCI Express 4x
interface.
PCI Target
/ Master
PCI Express
4x BUS
Local Bus
Address
Data(Mem,I/O)
Reserved
(0x00
?
0x5F)
Reserved
(0x70
?
0xAF)
UART
(0x60)
Camera Link(LVDS)
(0xC0)
Interrupt controller
DIO
(0xD0)
Ext. Address, Data, Control
Local BUS
Interrupt
Controller
(0xb0)
INT sources in Chip
IO Decoder
MEM Decoder
To each IO
Module
PCIe-FRM24 INTERNAL BLOCK - FPGA
DPRAM
From Ext.
CLOCK syn.
MEM Decoder
BUS Mux
Reserved
(0xE0
?
0xFF)
[Figure 2-1. Functional Block Diagram]
The core logic program of the FPGA is loaded by JTAG. It saves a program at the FPGA Program
Logic and loads when power-up.