NET-FRM01 Users Manual (Rev 1.3)
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http://www.daqsystem.com
3.2 Functional Blocks
(1)
FPGA : U5
All of the functions are controlled by the logic program of the FPGA.
(2)
DDR Memory : REF1, REF2
After save the data in a frame unit, transfer to PC through FPGA.
(3)
Oscillator : REF4, Y1
10/100/1000Mbps Ethernet Transceiver provides a 25MHz clock.
50MHz is supplied to the FPGA.
(4)
Ethernet Module
: REF5
10/100/1000Mbps Ethernet Module (RJ-45 Connector)
(5)
10/100/1000Mbps Ethernet Transceiver : REF6
The Ethernet Physical Layer of 1000BASE-T is executed.
(6)
Regulator : U1, U2,
The Regulator is for supplying the power (3.3V) to the board.
(7)
LVDS Channel : U3
It is protected a circuit that the interface of high voltage higher than 3.3V CMOS Logic is
exchanged to normal 3.3V Logic Level.
