54
PRELIMINARY
1M28, 1M75, and 1M150 User’s Manual
03-32-00525-04
DALSA
Table 25: EEPROM Functions and Assignment to Internal FPGA Register
PROM
Address
FPGA
Register
Address
Default
Name
Description
R/W
or C
HEX
HEX
HEX
EEPROM
EEPROM size
-
0
-
06
MODE0[7:0]
Mode register 0
R/W
1
6
13
MODE1[7:0]
Mode register 1
R/W
2
7
00
Sys_Ctl_LSB
LSB DAC0 System
Control Register
W
3
8
60
Sys_Ctl_MSB
MSB DAC0 System
Control Register
W
4
9
00
Chan0_Ctl_LSB
LSB DAC0 Channel
Register 0
W
5
8
10
Chan0_Ctl_MSB
MSB DAC0 Channel
Register 0
W
6
9
42
Chan1_Ctl_LSB
LSB DAC0 Channel
Register 1
W
7
8
10
Chan1_Ctl_MSB
MSB DAC0 Channel
Register 1
W
8
9
46
Chan2_Ctl_LSB
LSB DAC0 Channel
Register 2
W
9
8
10
Chan2_Ctl_MSB
MSB DAC0 Channel
Register 2
W
A
9
4A
Chan3_Ctl_LSB
LSB DAC0 Channel
Register 3
W
B
8
10
Chan3_Ctl_MSB
MSB DAC0 Channel
Register 3
W
C
9
4E
Chan4_Ctl_LSB
LSB DAC0 Channel
Register 4
W
D
8
10
Chan4_Ctl_MSB
MSB DAC0 Channel
Register 4
W
E
9
52
Chan5_Ctl_LSB
LSB DAC0 Channel
Register 5
W
F
8
10
Chan5_Ctl_MSB
MSB DAC0 Channel
Register 5
W
10
9
56
Chan6_Ctl_LSB
LSB DAC0 Channel
Register 6
W
11
8
10
Chan6_Ctl_MSB
MSB DAC0 Channel
Register 6
W
12
9
5A
Chan7_Ctl_LSB
LSB DAC0 Channel
Register 7
W
13
8
10
Chan7_Ctl_MSB
MSB DAC0 Channel
Register 7
W
14
9
5E
Chan0_Main_LSB
LSB DAC0 Channel 0
Main register
W
15
8
D7
(**)
Chan0_Main_MSB
MSB DAC0 Channel 0
Main register
W
16
9
20
(**)
Chan0_Sub_LSB
LSB DAC0 Channel 0
Sub register
W
17
8
00
(**)
Chan0_Sub_MSB
MSB DAC0 Channel 0
Sub register
W
18
9
A0
(**)
Chan1_Main_LSB
LSB DAC0 Channel 1
W
19
8
93
(**)
Abbreviations:
R: Read
W: Write
C: Command
DEC: Decimal value
HEX: Hexadecimal value
(
*
): bit 2 to bit 7
arbitrary value
(**)
: adjusted value