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DS12885/DS12887/DS12887A/DS12C887/DS12C887A

Real-Time Clock

____________________________________________________________________

PACKAGE

THETA-JA (°C/W)

THETA-JC (°C/W)

PDIP

105

PLCC

Thermal Information

PIN-PACKAGE DOCUMENT

NO.

24 SO (300 mils)

56-G4009-001

24 PDIP

56-G5000-003

24 EDIP

56-G0001-001

28 PLCC

56-G4001-001

32 TQFP

56-G4004-001

Package Information

Chip Information

TRANSISTOR COUNT: 17,000

PROCESS: CMOS

SUBSTRATE CONNECTED TO GROUND

TQFP

TOP VIEW

MOT

N.C.

SQW

N.C.

AD6

AD7

N.C.

GND

N.C.

R/W

23 N.C.

24 RCLR

BAT

IRQ

N.C.

RESET

GND

AD5

AD4

N.C.

AD3

N.C.

AD2

AD1

AD0

DS12885T

Pin Configurations (continued)

Ordering Information

PART TEMP

RANGE

PIN-
PACKAGE

TOP

MARK*

DS12885

0°C to +70°C

24 PDIP

DS12885

0°C to +70°C

24 PDIP

DS12885

DS12885N

-40°C to +85°C

24 PDIP

DS12885

-40°C to +85°C

24 PDIP

DS12885

DS12885Q

0°C to +70°C

28 PLCC

DS12885Q

0°C to +70°C

28 PLCC

DS12885Q

DS12885QN

-40°C to +85°C

28 PLCC

DS12885Q

-40°C to +85°C

28 PLCC

DS12885Q

DS12885Q/T&R

0°C to +70°C

28 PLCC

DS12885Q

DT&R

0°C to +70°C

28 PLCC

DS12885Q

DS12885QN/T&R

-40°C to +85°C

28 PLCC

DS12885Q

DST&R -40°C to +85°C

28 PLCC

DS12885Q

DS12885S

0°C to +70°C

24 SO
(300 mils)

DS12885S

0°C to +70°C

24 SO
(300 mils)

DS12885S

DS12885SN -40°C

+85°C

24 SO
(300 mils)

DS12885S

DS -40°C

+85°C

24 SO
(300 mils)

DS12885S

DS12885S/T&R

0°C to +70°C

24 SO
(300 mils)

DS12885S

DT&R

0°C to +70°C

24 SO
(300 mils)

DS12885S

DS12885T

0°C to +70°C

32 TQFP

DS12885

0°C to +70°C

32 TQFP

DS12885

DS12885TN

-40°C to +85°C

32 TQFP

DS12885

-40°C to +85°C

32 TQFP

DS12885

DS12885T/T&R

0°C to +70°C

32 TQFP

DS12885

DS12887

0°C to +70°C

24 EDIP

DS12887

0°C to +70°C

24 EDIP

DS12887

DS12887A

0°C to +70°C

24 EDIP

DS12887A

0°C to +70°C

24 EDIP

DS12887A

DS12C887

0°C to +70°C

24 EDIP

DS12C887

0°C to +70°C

24 EDIP

DS12C887

DS12C887A

0°C to +70°C

24 EDIP

DS12C887A

0°C to +70°C

24 EDIP

DS12C887A

Denotes a lead-free/RoHS-compliant device.

T&R = Tape-and-reel.

*A “+” anywhere on the top mark indicates a lead-free device,
and an “N” indicates an industrial temperature range device.

Содержание Maxim DS12885

Страница 1: ...AT Computer Clock Calendar RTC Counts Seconds Minutes Hours Day Date Month and Year with Leap Year Compensation Through 2099 Binary or BCD Time Representation 12 Hour or 24 Hour Clock with AM and PM i...

Страница 2: ...densing 0 C to 70 C Operating Temperature Range Industrial noncondensing 40 C to 85 C Storage Temperature Range 55 C to 125 C Soldering Temperature See IPC JEDEC J STD 020 Specification Note 1 Solderi...

Страница 3: ...ITS Cycle Time tCYC 385 DC ns Pulse Width DS Low or R W High PWEL 150 ns Pulse Width DS High or R W Low PWEH 125 ns Input Rise and Fall tR tF 30 ns R W Hold Time tRWH 10 ns R W Setup Time Before DS E...

Страница 4: ...________________________________ PWASH PWEL tASED tCYC tRWS tCS tRWH tCH PWEH tASD AD0 AD7 READ CS R W AS DS AD0 AD7 WRITE tDHW tDHR tDDR tAHL tASL tDSW Motorola Bus Read Write Timing Intel Bus Write...

Страница 5: ...__________________ 5 tCS tAHL tASL tCYC PWASH PWEL PWEH CS R W AS DS AD0 AD7 tASD tASD tASED tDDR tDHR tCH Intel Bus Read Timing tRWL tIRR tIRDS DS RESET IRQ IRQ Release Delay Timing OUTPUTS INPUTS HI...

Страница 6: ...mum and VIH minimum Input Pulse Rise and Fall Times 5ns WARNING Negative undershoots below 0 3V while the part is in battery backed mode may cause loss of data Note 1 RTC modules can be successfully p...

Страница 7: ...32768 60 32768 70 32768 00 4 5 5 5 IBAT1 vs VBAT vs TEMPERATURE DS12885 toc01 VBAT V I BAT nA 3 8 2 8 3 0 3 3 3 5 200 300 250 150 2 5 4 0 VCC 0V 85 C 25 C 0 C 40 C 70 C 40 C POWER CONTROL GND OSC BUS...

Страница 8: ...S transitions high in the case of Intel timing 12 16 12 15 20 12 17 GND Ground 13 13 16 13 CS Active Low Chip Select Input The chip select signal must be asserted low for a bus cycle in the device to...

Страница 9: ...tive Low Reset Input The RESET pin has no effect on the clock calendar or RAM On power up the RESET pin can be held low for a time to allow the power supply to stabilize The amount of time that RESET...

Страница 10: ...attery directly to the VBAT pin Diodes in series between the VBAT pin and the battery may prevent proper operation UL recognized to ensure against reverse charging when used with a lithium battery 21...

Страница 11: ...uit does not require any external resistors or capacitors to operate Table 1 specifies several crys tal parameters for the external crystal Figure 1 shows a functional schematic of the oscillator circ...

Страница 12: ...bytes can be either binary or binary coded decimal BCD format The day of week register increments at midnight incre menting from 1 through 7 The day of week register is used by the daylight saving fu...

Страница 13: ...or read except for the following 1 Registers C and D are read only 2 Bit 7 of register A is read only 3 The MSB of the seconds byte is read only Table 2A Time Calendar and Alarm Data Modes BCD Mode DM...

Страница 14: ...0 0 Day Day 01 07 07H 0 0 0 Date Date 01 1F 08H 0 0 0 0 Month Month 01 0C 09H 0 Year Year 00 63 0AH UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0 Control 0BH SET PIE AIE UIE SQWE DM 24 12 DSE Control 0CH IRQF PF A...

Страница 15: ...ime A pattern of 11x enables the oscillator but holds the countdown chain in reset The next update occurs at 500ms after a pattern of 010 is written to DV0 DV1 and DV2 Bits 3 to 0 Rate Selector RS3 RS...

Страница 16: ...te end flag UF bit in Register C to assert IRQ The RESET pin going low or the SET bit going high clears the UIE bit The internal functions of the device do not affect the UIE bit but is cleared to 0 o...

Страница 17: ...in goes low and a 1 appears in the IRQF bit This bit can be cleared by reading Register C or with a RESET Bit 5 Update Ended Interrupt Flag UF This bit is set after each update cycle When the UIE bit...

Страница 18: ...at are set high are cleared when read and new interrupts that are pending during the read cycle are held until after the cycle is completed One two or three bits can be set when reading Register C Eac...

Страница 19: ...s read on the UIP bit the user has at least 244 s before the time calendar data is changed Therefore the user should avoid interrupt service rou tines that would cause the time needed to read valid ti...

Страница 20: ...C N C MOT N C IRQ RESET DS AD4 AD3 AD2 AD1 N C R W AS CS FOR THE DS12887A DS12C887A NOTE THE DS12887A AND DS12C887A CANNOT BE STORED OR SHIPPED IN CONDUCTIVE MATERIAL THAT WILL GIVE A CONTINUITY PATH...

Страница 21: ...DS12885QN 40 C to 85 C 28 PLCC DS12885Q DS12885QN 40 C to 85 C 28 PLCC DS12885Q DS12885Q T R 0 C to 70 C 28 PLCC DS12885Q DS12885Q T R 0 C to 70 C 28 PLCC DS12885Q DS12885QN T R 40 C to 85 C 28 PLCC...

Страница 22: ...trademark of Dallas Semiconductor Corporation Quijano Revision History Rev 0 6 05 Initial release of combined data sheet Rev 1 4 06 Corrected Intel Bus Write Timing diagram page 4 Intel Bus Read Timin...

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