How to Use A/D Converter for S6J3110/ S6J3120 Series
Document No. 002-04457 Rev. *B
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3.5.1.2 A/D Converter Time Setting
The A/D converter time setting uses A/D Mode Setting Register. (ADMD) The A/D Converter time setting depends on
Compare time and Sampling time. And this register selects whether to set sampling time for A/D conversion for each
channel or to set a common setting.
Figure 6. A/D Converter Time Setting Flow
Note:
* When the peripheral clock is 36MHz operation on S6J311E.
Sampling time setting
(48 peripheral clock cycles:1.3µs* )
ADC0_ADMD0_ST=3
Common sampling time setting to all channels
ADC0_ADMD0_STPCEN=0
A/D Converter time setting
End
Compare time setting
(28 peripheral clock cycles:0.8µs* )
ADC0_ADMD0_CT=0