Document Number: 002-00948 Rev. *C
S29CD032J
S29CD016J
S29CL032J
S29CL016J
7.8.5 DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5
produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed.
The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. Only an
erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a 1.
Under both these conditions, the system issues the reset command to return the device to reading array data.
7.8.6 DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The
sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the
time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not
monitor DQ3. See
After the sector erase command is written, the system reads the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that
the device has accepted the command sequence, then reads DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all
further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device accepts
additional sector erase commands.
To ensure the command has been accepted, the system software check the status of DQ3 prior to and following each sub-sequent
sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted.
shows the status of DQ3 relative to the other status bits.
7.8.7 RY/BY#: Ready/Busy#
The device provides a RY/BY# open drain output pin as a way to indicate to the host system that the Embedded Algorithms are
either in progress or have been completed. If the output of RY/BY# is low, the device is busy with either a program, erase, or reset
operation. If the output is floating, the device is ready to accept any read/write or erase operation. When the RY/BY# pin is low, the
device will not accept any additional program or erase commands with the exception of the Erase suspend command. If the device
has entered Erase Suspend mode, the RY/BY# output is floating. For programming, the RY/BY# is valid (RY/BY# = 0) after the
rising edge of the fourth WE# pulse in the four write pulse sequence. For chip erase, the RY/BY# is valid after the rising edge of the
sixth WE# pulse in the six write pulse sequence. For sector erase, the RY/BY# is also valid after the rising edge of the sixth WE#
pulse.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is
complete, which requires a time of t
READY
(during Embedded Algorithms). The system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is
floating), the reset operation is completed in a time of t
READY
(not during Embedded Algorithms). The system can read data t
RH
after
the RESET# pin returns to V
IH
.
Since the RY/BY# pin is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to V
CC
. An
external pull-up resistor is required to take RY/BY# to a V
IH
level since the output is an open drain.
shows the outputs for RY/BY#, DQ7, DQ6, DQ5, DQ3 and DQ2.
,
, and
show RY/
BY# for read, reset, program, and erase operations, respectively.
