Document Number: 002-00948 Rev. *C
S29CD032J
S29CD016J
S29CL032J
S29CL016J
Figure 25. Program Operation Timings
Note
70.PA = program address, PD = program data, D
OUT
is the true data at the program address.
Figure 26. Chip/Sector Erase Operation Timings
Note
71.SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see
Write Operation Status on page 32
OE#
WE#
CE#
V
CC
Data
Addresses
t
DS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
t
VCS
555h
PA
PA
Read Status Data (last two cycles)
A0h
t
CS
Status
D
OUT
Program Command Sequence (last two cycles)
RY/BY#
t
RB
t
BUSY
t
CH
PA
t
DH
OE#
CE#
Addresses
V
CC
WE#
Data
2AAh
SA
t
WP
t
WC
t
AS
t
WPH
555h for chip erase
10 for Chip Erase
30h
t
DS
t
VCS
t
CS
t
DH
t
CH
In
Progress
Complete
t
WHWH2
VA
VA
Erase Command Sequence (last two cycles)
Read Status Data
RY/BY#
t
RB
t
BUSY
t
DH
t
AH