Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

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40 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
RAM Paging
4.1.2 Stack Operations
As mentioned previously, the paging architecture's reset
state puts the in a mode identical to that of a 256-byte
device. Therefore, upon reset, all memory accesses are to
Page 0. The SRAM page that stack operations use is deter-
mined by the value of the three least significant bits (LSb) of
the Stack Page Pointer register (STK_PP). Stack operations
have no dependency on the PgMode bits in the CPU_F reg-
ister. Stack operations are those that use the Stack Pointer
(SP) to calculate their affected address. Refer to the
PSoC
Designer Assembly Language User Guide for more informa-
tion on all M8C instructions.
Stack memory accesses are a special case. If they were not,
the stack could fragment across several pages. To prevent
the stack from fragmenting, all instructions that operate on
the stack automatically use the page indicated by the
STK_PP register. Therefore, if the program encounters a
CALL, the PSoC device automatically pushes the program
counter onto the stack page indicated by STK_PP. After the
program counter is pushed, the SRAM paging mode auto-
matically switches back to the precall mode. All other stack
operations, such as
RET
and
POP
, follow the same rule as
CALL
. The stack is confined to a single SRAM page and the
Stack Pointer wraps from 00h to FFh and FFh to 00h. The
user code must ensure that the stack is not damaged
because of stack wrapping.
Because the value of the STK_PP register can change at
any time, it is theoretically possible to manage the stack in
such a way as to allow it to grow beyond one SRAM page or
manage multiple stacks. However, the only supported use of
the STK_PP register is when its value is set before the first
stack operation and not changed again.
4.1.3 Interrupts
Interrupts, in a multipage SRAM PSoC device, operate the
same as interrupts in a 256-byte device. However, because
the CPU_F register is automatically set to 0x00 on an inter-
rupt and because of the nonlinear nature of interrupts in a
system, other parts of the memory paging architecture can
be affected.
Interrupts are an abrupt change in program flow. If no spe-
cial action is taken on interrupts by the PSoC device, the
interrupt service routine (ISR) could be thrown into any
SRAM page. To prevent this problem, the special address-
ing modes for all memory accesses, except for stack and
MVI , are disabled when an ISR is entered. The special
addressing modes are disabled when the CUP_F register is
cleared. At the end of the ISR, the previous SRAM address-
ing mode is restored when the CPU_F register value is
restored by the
RETI
instruction.
All interrupt service routine code starts execution in SRAM
Page 0. If the ISR must change to another SRAM page, do
this by changing the values of the CPU_F[7:6] bits to enable
the special SRAM addressing modes. However, any change
made to the CUR_PP, IDX_PP, or STK_PP registers per-
sists after the ISR returns. Therefore, have the ISR save the
current value of any paging register it modifies and restore
its value before the ISR returns.
4.1.4 MVI Instructions
MVI instructions use data page pointers of their own
(MVR_PP and MVW_PP). This allows a data buffer to be
located away from other program variables, but accessible
without changing the Current Page Pointer (CUR_PP).
An
MVI
instruction performs three memory operations. Both
forms of the
MVI
instruction access an address in SRAM
that holds the data pointer (a memory read 1st access),
incrementing that value and then storing it back in SRAM (a
memory write 2nd access). This pointer value must reside in
the current page, just as all other nonstack and nonindexed
operations on memory. However, the third memory opera-
tion uses the MVx_PP register. This third memory access is
either a read or a write, depending upon which
MVI instruc-
tion is used. The MVR_PP pointer is used for the
MVI
instruction that moves data into the accumulator. The
MVW_PP pointer is used for the
MVI
instruction that moves
data from the accumulator into SRAM. The
MVI
pointers are
always enabled, regardless of the state of the Flag register
page bits (CPU_F register).
4.1.5 Current Page Pointer
The Current Page Pointer determines which SRAM page is
used for all memory accesses. Normal memory accesses
are those not covered by other pointers including all non-
stack, non-
MVI
, and nonindexed memory access instruc-
tions. The normal memory access instructions have the
SRAM page they operate on determined by the value of the
CUR_PP register. By default, the CUR_PP register has no
affect on the SRAM page that is used for normal memory
access, because all normal memory access is forced to
SRAM Page 0.
The upper bit of the PgMode bits in the CPU_F register
determine if the CUR_PP register affects normal memory
access. When the upper bit of the PgMode bits is set to ‘0’,
all normal memory access is forced to SRAM Page 0. This
mode is automatically enabled when an Interrupt Service
Routine (ISR) is entered. This is because, before the ISR is
entered, the M8C pushes the current value of the CPU_F
register onto the stack and then clears the CPU_F register.
Therefore, by default, any normal memory access in an ISR
is guaranteed to occur in SRAM Page 0.
When the
RETI
instruction is executed to end the ISR, the
previous value of the CPU_F register is restored, returning
to the previous page mode. This is the default ISR behavior
and that it is possible to change the PgMode bits in the
CPU_F register while in an ISR. If the PgMode bits are
changed while in an ISR, the pre-ISR value is still restored
by the
RETI
; but if the CUR_PP register is changed in the
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