PSoC™ 6 Wi-Fi Bluetooth® pioneer kit guide, Document Number. 002-22677 Rev. *I
22
2.
Kit operation
This chapter introduces you to various features of the PSoC™ 6 Wi-Fi Bluetooth
®
pioneer board,
including the theory of operation and the on-board KitProg3 programming and debugging
functionality, USB-UART, USB-I2C and USB-SPI bridges.
2.1
Theory of operation
The PSoC™ 6 Wi-Fi Bluetooth
®
pioneer kit is built around the PSoC™ 6 MCU;
shows the
block diagram of the device. For details of the PSoC™ 6 MCU features, see the
Figure 2-1. PSoC™ 6 MCU block diagram
System
Hibernate Mode
Backup
Domain
System
DeepSleep Mode
System LP/ULP Mode
CPUs Active/Sleep
Color Key:
Power Modes and
Domains
PSoC 62 MCU
CY8C62x6, CY8C62x7
CPU Subsystem
Audio Subsystem
SCB
Programmable Analog
SAR ADC 12 bit
SARMUX
DAC 12 bit
2x Opamp
Temperature Sensor
Programmable Digital: 12x UDB
DSI
I/O Subsystem:
Up to 100 GPIOs (including 6 OVT), 124
-BGA Package
Boundary Scan
2x Smart I/O Ports
USB
PHY
System Interconnec
t (Multi Layer AH
B, IPC, MPU/SMPU)
Cortex M4F CPU
150/50 MHz, 1.1/0.9 V
SWJ, ETM, ITM, CTI
Cortex M0+ CPU
100/25 MHz, 1.1/0.9 V
SWJ, MTB, CTI
2x DMA
Controller
Crypto
DES/TDES, AES, SHA,
CRC, TRNG, RSA/ECC
Accelerator
Flash
1024 KB + 32 KB + 32 KB
8 KB cache for each CPU
SRAM
288 KB
ROM
128 KB
Peripheral Interconnect (MMIO, PPU)
Peripheral clock (
cl
k_
pe
ri
)
System Resources
Power
Clocks
POR
LVD
BOD
OVP
Buck Regulator
WCO
RTC
IMO
WDT
2x PLL
ECO
ILO
FLL
2x MCWDT
Backup Regs
XRES Reset
PMIC Control
PILO