CY8CKIT-149 PSoC® 4100S Plus Prototyping Kit Guide, Doc. #: 002-20729 Rev. *E
41
A.2.5.3
Functionality of J6 and J7 Headers (KitProg2)
The KitProg2 board contains two single inline headers (
J6
and
J7
). Both are 1x7-pin-headers, used
to pull out several pins of the PSoC 5LP to support advanced features like a low-speed oscilloscope
and a low-speed digital logic analyzer. This header also contains the KitProg2 bridge pins that can
be used when the two boards are separated.
The
J6
and
J7
headers support 100-mil spacing, so you can solder connectors to connect the
KitProg2 board to a development breadboard.
Figure A-7. J6 and J7 Headers
Table A-5. Pin Details of J6
Table A-6. Pin Details of J7
PSoC 5LP KitProg2 Header (J6)
Pin
Signal
Description
J6_01
VBUS
Power
J6_02
GND
Ground
J6_03
P12.5
GPIO
J6_04
P12.0
GPIO/I2C_SCL
J6_05
P12.1
GPIO/I2C_SDA
J6_06
P12.7
GPIO/UART_RX
J6_07
P12.6
GPIO/UART_TX
PSoC 5LP KitProg2 Header (J7)
Pin
Signal
Description
J7_01
GND
Ground
J7_02
P3.0
GPIO
J7_03
P3.4
GPIO
J7_04
P3.5
GPIO
J7_05
P3.6
GPIO
J7_06
P0.2
GPIO
J7_07
P0.1
GPIO