Cypress MB96640 Series, Руководство пользователя

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Document Number: 002-04713 Rev.*A Page 2 of 65
MB96640 Series

Hardware Watchdog Timer
 Hardware watchdog timer is active after reset

Window function of Watchdog Timer is used to select the
lower window limit of the watchdog interval

Reload Timers

16-bit wide
 Prescaler with 1/2
1
, 1/2
2
, 1/2
3
, 1/2
4
, 1/2
5
, 1/2
6
of peripheral
clock frequency
 Event count function

Free-Running Timers

Signals an interrupt on overflow, supports timer clear upon
match with Output Compare (0, 4)

Prescaler with 1, 1/2
1
, 1/2
2
, 1/2
3
, 1/2
4
, 1/2
5
, 1/2
6
, 1/2
7
, 1/2
8
of peripheral clock frequency

Input Capture Units

16-bit wide
 Signals an interrupt upon external event

Rising edge, Falling edge or Both (rising & falling) edges
sensitive

Output Compare Units

16-bit wide
 Signals an interrupt when a match with Free-running Timer
occurs
 A pair of compare registers can be used to generate an
output signal

Programmable Pulse Generator
 16-bit down counter, cycle and duty setting registers

Can be used as 2 × 8-bit PPG
 Interrupt at trigger, counter borrow and/or duty match
 PWM operation and one-shot operation
 Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral
clock as counter clock or of selected Reload timer
underflow as clock input

Can be triggered by software or reload timer
 Can trigger ADC conversion

Timing point capture
 Start delay

Quadrature Position/Revolution Counter (QPRC)

Up/down count mode, Phase difference count mode,
Count mode with direction
 16-bit position counter
 16-bit revolution counter

Two 16-bit compare registers with interrupt
 Detection edge of the three external event input pins AIN,
BIN and ZIN is configurable

Real Time Clock
 Operational on main oscillation (4MHz), sub oscillation
(32kHz) or RC oscillation (100kHz/2MHz)
 Capable to correct oscillation deviation of Sub clock or RC
oscillator clock (clock calibration)
 Read/write accessible second/minute/hour registers
 Can signal interrupts every half
second/second/minute/hour/day

Internal clock divider and prescaler provide exact 1s clock

External Interrupts
 Edge or Level sensitive

Interrupt mask bit per channel
 Each available CAN channel RX has an external interrupt
for wake-up
 Selected USART channels SIN have an external interrupt
for wake-up

Non Maskable Interrupt
 Disabled after reset, can be enabled by Boot-ROM
depending on ROM configuration block
 Once enabled, cannot be disabled other than by reset

High or Low level sensitive
 Pin shared with external interrupt 0

I/O Ports

Most of the external pins can be used as general purpose
I/O

All push-pull outputs (except when used as I
2
C SDA/SCL
line)

Bit-wise programmable as input/output or peripheral signal
 Bit-wise programmable input enable

One input level per GPIO-pin (either Automotive or CMOS
hysteresis)

Bit-wise programmable pull-up resistor

Built-in On Chip Debugger (OCD)
 One-wire debug tool interface

Break function:
• Hardware break: 6 points (shared with code event)
• Software break: 4096 points
 Event function
• Code event: 6 points (shared with hardware break)
• Data event: 6 points
• Event sequencer: 2 reset
 Execution time measurement function
 Trace function: 42 branches

Security function

Flash Memory
 Dual operation flash allowing reading of one Flash bank
while programming or erasing the other bank
 Command sequencer for automatic execution of
programming algorithm and for supporting DMA for
programming of the Flash Memory

Supports automatic programming, Embedded Algorithm
 Write/Erase/Erase-Suspend/Resume commands
 A flag indicating completion of the automatic algorithm
 Erase can be performed on each sector individually

Sector protection
 Flash Security feature to protect the content of the Flash

Low voltage detection during Flash erases or writes