Document Number: 002-04713 Rev.*A
Page 6 of 65
MB96640 Series
2. Block Diagram
I
2
C
2ch
SDA0, SDA1
SCL0, SCL1
DMA
Controller
Boot ROM
Peripheral
Bus Bridge
Peripheral
Bus Bridge
16FX Core Bus (CLKB)
USART
6ch
8/10-bit ADC
24ch
I/O Timer 0
ICU 0/1
CAN
Interface
1ch
Real Time
Clock
Watchdog
RAM
Voltage
Regulator
SIN0, SIN1, SIN2, SIN4, SIN5, SIN7, SIN5_R, SIN7_R
SOT0, SOT1, SOT2, SOT4, SOT7, SOT5_R, SOT7_R
SCK0, SCK1, SCK2, SCK4, SCK7, SCK5_R, SCK7_R
FRCK0, FRCK0_R
IN0, IN0_R, IN1_R
TX0
Vcc
Vss
C
16FX
CPU
Interrupt
Controller
Clock &
Mode Controller
Flash
Memory A
NMI
16-bit Reload
Timer
0/1/2/3/6
TIN0 to TIN3
TOT0 to TOT3
PPG0, PPG1, PPG3 to PPG7
TTG0, TTG2 to TTG4, TTG6, TTG7, TTG12 to TTG14
CKOT0_R, CKOT1, CKOT1_R
CKOTX0, CKOTX1, CKOTX1_R
X0, X1
X0A, X1A
RSTX
MD
PPG
16ch (16-bit)/
24ch (8-bit)
I/O Timer 1
ICU 4/5/6/7
FRCK1
IN6, IN7
External
Interrupt
INT0 to INT15
INT1_R to INT7_R
OCD
DEBUG I/F
WOT, WOT_R
AVss
AVRH
AN2 to AN4, AN6 to AN8
RX0
AVcc
P
e
ri
p
h
e
ra
l
B
u
s
2
(C
L
K
P
2
)
Pe
ri
p
h
e
ra
l
B
u
s
1
(C
LK
P
1
)
I/O Timer 2
ICU 9
OCU 0/1/2/3
OUT0 to OUT3
OUT0_R, OUT2_R
OCU 4/6/7
OUT6, OUT7
AVRL
PPG0_R to PPG4_R, PPG8_R to PPG13_R
PPG4_B to PPG11_B, PPG14_B, PPG15_B
QPRC
2ch
AIN0, AIN1
ZIN0, ZIN1
BIN0, BIN1
IN4_R, IN5_R, IN7_R
FRCK2
ADTG
AN10 to AN12, AN14 to AN28
FRT 0
FRT 1
FRT 2
16ch
5ch