Cypress FR81S CY91520 Series Скачать руководство пользователя страница 32

 

Recommendation for Hardware Setup 32-Bit FR81S Family 

www.cypress.com

 

Document No. 002-09375 Rev. *B 

32 

Worldwide Sales and Design Support 

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the 
office closest to you, visit us a

Cypress Locations

Products 

Arm

®

 Cortex

®

 Microcontrollers 

cypress.com/arm

 

Automotive 

cypress.com/automotive

 

Clocks & Buffers 

cypress.com/clocks

 

Interface 

cypress.com/interface

 

Internet of Things 

cypress.com/iot

 

Memory  

cypress.com/memory

 

Microcontrollers 

cypress.com/mcu

 

PSoC 

cypress.com/psoc

 

Power Management ICs 

cypress.com/pmic

 

Touch Sensing 

cypress.com/touch

 

USB Controllers 

cypress.com/usb

 

Wireless Connectivity 

cypress.com/wireless

 

PSoC® Solutions 

PSoC 1

 

PSoC 3

 

PSoC 4

 

PSoC 5LP

 | 

PSoC 6 MCU  

Cypress Developer Community 

Community

  

Projects

  

Videos

  | 

Blogs

  

Training 

Components

 

Technical Support 

cypress.com/support

 

 

 Cypress Semiconductor 

 198 Champion Court 

 San Jose, CA 95134-1709 

© Cypress Semiconductor Corporation, 2013-2019. 

This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”).  

This  document,  including  any  software  or  firmware  incl

uded  or  referenced in  this  document (“Software”),  is  owned by  Cypress  under  the  intellectual 

property laws and treaties of the United States and other countries worldwide.  Cypress reserves all rights under such laws and treaties and does not, 
except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights.  If the 
Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, 
then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the 
Software  (a)  for  Software  provided  in  source  code  form,  to  modify  and  reproduce  the  Software  solely  for  use  with  Cypress  hardware  products,  only 
internally  within  your  organization,  and  (b)  to  distribute  the  Software  in  binary  code  form  externally  to  end  users  (either  directly  or  indirectly  through 
resellers and distri

butors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the 

Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products.  Any 
other use, reproduction, modification, translation, or compilation of the Software is prohibited. 

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD 
TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  No computing device can be absolutely secure.  Therefore, despite security 
measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such as unauthorized 
access  to  or  use  of  a  Cypress  product.    CYPRESS  DOES  NOT  REPRESENT,  WARRANT,  OR  GUARANTEE  THAT  CYPRESS  PRODUCTS,  OR 
SYSTEMS CREATED USING CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA 
LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security Breach”).  Cypress disclaims any liability relating to any Security Breach, 
and  you  shall  and  hereby  do  release  Cypress  from  any  claim,  damage,  or  other  liability  arising  from  any  Security  Breach.    In  addition,  the  products 
described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications.  
To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume 
any liability arising out of the application or use of any product or circuit described in this document.  Any information provided in this document, including 
any sample design information or programming code, is provided only for reference purposes.  It is the responsibility of the  user of this document to 
properly design, pro

gram, and test the functionality and safety of any application made of this information and any resulting product.  “High-Risk Device” 

means any device or system whose failure could cause personal injury, death, or property damage.  Examples of High-Risk Devices are weapons, nuclear 
installations, surgical implants, and other medical devices.  “Critical Component” means any component of a High-Risk Device whose failure to perform 
can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect its safety or effectiveness.  Cypress is not 
liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product 
as a Critical Component in a High-Risk Device.  You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, 
and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal 
injury or death, or property damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device.  Cypress products are not 
intended or authorized for use as a Critical Component in any High-Ris

k Device except to the limited extent that (i) Cypress’s published data sheet for the 

product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization 
to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement. 

Cypress,  the  Cypress  logo,  Spansion,  the  Spansion  logo,  and  combinations  thereof,  WICED,  PSoC,  CapSense,  EZ-USB,  F-RAM,  and  Traveo  are 
trademarks  or  registered  trademarks  of  Cypress  in  the  United  States  and  other  countries.    For  a  more  complete  list  of  Cypress  trademarks,  visit 
cypress.com.  Other names and brands may be claimed as property of their respective owners. 

Содержание FR81S CY91520 Series

Страница 1: ...nded Power Supply Circuit 12 3 7 Reset circuit 13 3 8 Quartz Crystal Placement and Signal Routing 16 3 9 Test points 18 3 10 Other documents 18 4 Port Input Unused Pins Latch up 19 4 1 Port Input Unus...

Страница 2: ...ist The MAX232 is a standard level shifter which converts the 5 V levels of the MCU to 12V RS232V24 levels and vice versa If you use a 3 3 V system a MAX3232 is recommended Please consider that the in...

Страница 3: ...capacitor Cext approx 0 1 F to the analog input pin An input impedance maximum Rext 15k Ohm is recommended So an appropriate sample time has to be selected depending on the impedance Rext and the capa...

Страница 4: ...dance may cause latch up effects together with an RSTX Switch and low EMI protection The reset level of RSTX pins depends on the logical level on NMIX pin Please refer to Hardware manual chapter 7 Res...

Страница 5: ...GPIO GPIO OSC GPIO Vcc Vcc 5V Vcc Vss GND Vss GND 5V 5V 5V GND Vss GND Vcc Vss C Internal 1 2V Vss GND 4 7 F ceramic X7R CORE internal voltage regulator 1 Note 1 Vss pin closest to C pin 2 9 Clock So...

Страница 6: ...Handling devices for further information The following settings are used for the both modes mentioned above Table 3 Mode Pin Settings x does not care Mode P006 MD0 MD1 Serial Programming Mode 1 0 1 Ru...

Страница 7: ...k D1 e g HZM6 2Z4MFA E D2 schottky diode e g BAS40 Debug connector SMA 50R connector for development target boards Table 4 SPEED BOX General Specifications Item Specification MDI bus maximum communic...

Страница 8: ...have to be placed as near as possible to the X1 A pins output of the inverter The feedback resistor of oscillator circuit typ 1Mohm is already implemented internally The evaluation of crystal resonat...

Страница 9: ...ss of the whole circuit to avoid a ground loop Below is a principal example of a bad and a good power line routing Figure 5 Example of bad vs good power line routing For four and more layers PCB the V...

Страница 10: ...ls BAD crosstalk between different power supply planes GND Avcc Vcc low speed signals high speed signals GOOD separation of power supply planes for low EMC requirements 3 5 Power Supply Decoupling DeC...

Страница 11: ...oards is recommended Figure 8 Power Supply decoupling on single side assembled boards L4 L3 VCC L2 GND L1 MCU VCC VSS MCU CB The following routing and placement for multi layer PCB is recommended Note...

Страница 12: ...d IO pins like stepper motor controller or external bus interface can generate spikes on the supplies These are difficult to filter using capacitors only A series inductor ferrite e g WE742792022 is t...

Страница 13: ...ard reset extension circuit to guarantee the stabilization of the Low Voltage Detector LVD and complete reset of the device before program execution starts The reset signal at RSTX pin goes through a...

Страница 14: ...dware Setup 32 Bit FR81S Family www cypress com Document No 002 09375 Rev B 14 Please see also the datasheet chapter External reset timing of related MCU series Table 7 External reset timing Figure 12...

Страница 15: ...Recommendation for Hardware Setup 32 Bit FR81S Family www cypress com Document No 002 09375 Rev B 15 Figure 13 Block Diagram of reset extension circuit...

Страница 16: ...f MCU device The value of both load capacitors C1 C2 should be determined with crystal matching test The crystal matching test must be done by the crystal manufacturer based on the target board As a r...

Страница 17: ...pins Figure 16 Layout example for crystal oscillator circuit DeCap CB on backside Vias to Vcc plane on inner layers Vias to ground plane on inner layers Ground plane on inner layers X0 Vcc Vss CB SMD...

Страница 18: ...nctions for failure analysis in development mass production or in the field MONCLK out could be used e g for clock calibration of main or sub oscillator Figure 18 MONCLK internal clock select and pres...

Страница 19: ...define the input level If both solutions are not possible set the Port Pin to Output Never connect a potential divider with almost same resistor values Figure 19 Principle using of input circuit to a...

Страница 20: ...ground together with debouncing capacitors connected to port pins A usual configuration is shown in the following schematic Figure 20 Usual Configuration Switch RPD is a pull down resistor and CBD a d...

Страница 21: ...osing Point A But at the port pin Pxy on point B the following voltage can be measured Figure 23 Signal rise on switch closing Point B By closing the switch SW the circuit becomes a parallel oscillato...

Страница 22: ...on the port pin The frequency of the oscillation can be calculated by Equation Oscillation frequency DB X OSC C L f 2 1 The inductivity LX is the unknown value and depends on the PCB its routing and...

Страница 23: ...like in the following schematic Figure 27 Series resistor The series resistor RS reduces the amplitude of the oscillation and decreases the voltage offset at first The resistor must not be chosen too...

Страница 24: ...al VCC 3V 5V VCC VSS VSS IN OUT MCU Peripheral 5V tolerant input a Standard IO b 5 V Tolerant IO For 5 V Tolerant IO the diode is not attached to the Pch side It is a protection circuit in the parasit...

Страница 25: ...o achieve that nowadays you can do it in different ways using a regular serial cable if a DB9 serial connector is present in the computer or using a more modern USB cable i e FTDI TTL 232R http www ft...

Страница 26: ...stem as you can see in the Figure 31 using only one signal connected to pin MD0 inverting MD1 and a pull up resistor on the pin P006 Figure 31 Principal Schematic for serial programming via Usart0 Fla...

Страница 27: ...g is the MDI interface using only one signal pin Debug I F through the MB2100 01 E debugger The MB2100 01 E debugger is connected to the host computer with an USB cable and to the target PCB with a si...

Страница 28: ...B 28 Figure 34 Picture of the MB2100 01 E Figure 35 Electronic Components needed to protect the Debug I F pin VCC Debug Connector R1 ECU GND R2 D2 DEBUGIF MCU D1 GND R1 43 R R2 10 k D1 e g HZM6 2Z4MF...

Страница 29: ...e this function the user has to write in a specific flash memory location a password and a flash security code From then security is turned on and access restrictions are imposed on subsequent accesse...

Страница 30: ...ed HiZ If some external bus pins should be used as GPIO than do not use any address or bus control lines as input because these lines are driven as output high 7 Additional Information Information abo...

Страница 31: ...release RSTX and NMIX input section correction RSTX and NMIX input obsolete issue removed Added new section 5V tolerant IOs 01 06 2014 V1 3 FTo 02 11 2015 V1 4 FTo Modified Figure 1 Principle schemati...

Страница 32: ...ability arising out of any security breach such as unauthorized access to or use of a Cypress product CYPRESS DOES NOT REPRESENT WARRANT OR GUARANTEE THAT CYPRESS PRODUCTS OR SYSTEMS CREATED USING CYP...

Отзывы: