Cypress EZ-BLE PRoC CYBLE-212019-00, Руководство пользователя

Страница: 22 / 39

Document Number: 002-09764 Rev. *G Page 22 of 39
CYBLE-212019-00
CYBLE-212023-10
Serial Communication
Table 28. Fixed I
2
C DC Specifications
Table 30. Fixed UART DC Specifications
Table 31. Fixed UART AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
I
I2C1
Block current consumption at 100 kHz – – 50

A –
I
I2C2
Block current consumption at 400 kHz – – 155

A –
I
I2C3
Block current consumption at 1 Mbps – – 390

A –
I
I2C4
I
2
C enabled in Deep-Sleep mode – – 1.4

A –
Table 29. Fixed I
2
C AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
F
I2C1
Bit rate – – 400 kHz
Parameter Description Min Typ Max Units Details/Conditions
I
UART1
Block current consumption at 100 kbps – – 55

A –
I
UART2
Block current consumption at 1000 kbps – – 312

A –
Parameter Description Min Typ Max Units Details/Conditions
F
UART
Bit rate – – 1 Mbps –
Table 32. Fixed SPI DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
I
SPI1
Block current consumption at 1 Mbps – – 360

A –
I
SPI2
Block current consumption at 4 Mbps – – 560

A –
I
SPI3
Block current consumption at 8 Mbps – – 600

A –
Table 33. Fixed SPI AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
F
SPI
SPI operating frequency (master; 6x over sampling) – – 8 MHz –
Table 34. Fixed SPI Master Mode AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
T
DMO
MOSI valid after SCLK driving edge – – 18 ns –
T
DSI
MISO valid before SCLK capturing edge
Full clock, late MISO sampling used
20 – – ns Full clock, late MISO sampling
T
HMO
Previous MOSI data hold time 0 – – ns Referred to Slave capturing edge
Table 35. Fixed SPI Slave Mode AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
T
DMI
MOSI valid before SCLK capturing edge 40 – – ns
T
DSO
MISO valid after SCLK driving edge – – 42 + 3 × T
CPU
ns
T
DSO_ext
MISO Valid after SCLK driving edge in
external clock mode. V
DD
< 3.0 V
– – 50 ns
T
HSO
Previous MISO data hold time 0 – – ns
T
SSELSCK
SSEL valid to first SCK valid edge 100 – – ns