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Document Number: 002-09764 Rev. *G 

Page 23 of 39

CYBLE-212019-00
CYBLE-212023-10

Memory

System Resources

Power-on-Reset (POR) 

Table 36.  Flash DC Specifications

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

V

PE

Erase and program voltage

1.71

5.5

V

T

WS48

Number of Wait states at 32–48 MHz 

2

– 

CPU execution from flash

T

WS32

Number of Wait states at 16–32 MHz

1

– 

CPU execution from flash

T

WS16

Number of Wait states for 0–16 MHz

0

– 

CPU execution from flash

Table 37.  Flash AC Specifications

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

T

ROWWRITE

[9]

Row (block) write time (erase and program)

– 

– 

20

ms

Row (block) = 256 bytes

T

ROWERASE

[9]

Row erase time

13

ms

T

ROWPROGRAM

[9]

Row program time after erase

– 

– 

7

ms

T

BULKERASE

[9]

Bulk erase time (256 KB)

35

ms

T

DEVPROG

[9]

Total device program time

25

seconds

F

END

Flash endurance

100 K

– 

– 

cycles

F

RET

Flash retention. T

A

 

 55 °C, 100 K P/E cycles

20

years

F

RET2

Flash retention. T

A

 

 85 °C, 10 K P/E cycles

10

– 

– 

years

Table 38.  POR DC Specifications

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

V

RISEIPOR

Rising trip voltage

0.80

1.45

V

V

FALLIPOR

Falling trip voltage

0.75

1.40

V

V

IPORHYST

Hysteresis 15

200

mV

Table 39.  POR AC Specifications

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

T

PPOR_TR

Precision power-on reset (PPOR) response 
time in Active and Sleep modes

1

s

Table 40.  Brown-Out Detect

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

V

FALLPPOR

BOD trip voltage in Active and Sleep modes

1.64

– 

V

V

FALLDPSLP

BOD trip voltage in Deep Sleep

1.4

– 

V

Table 41.  Hibernate Reset

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

V

HBRTRIP

BOD trip voltage in Hibernate

1.1

– 

V

Note

9. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have 

completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make 
certain that these are not inadvertently activated.

Содержание EZ-BLE PRoC CYBLE-212019-00

Страница 1: ...re range 40 C to 85 C 32 bit processor 0 9 DMIPS MHz with single cycle 32 bit multiply operating at up to 48 MHz Watchdog timer with dedicated internal low speed oscillator ILO Two pin SWD for programming Power Consumption TX output power 18 dbm to 3 dbm Received signal strength indicator RSSI with 1 dB resolution TX current consumption of 15 6 mA radio only 0 dbm RX current consumption of 16 4 mA...

Страница 2: ...Design Environment IDE that enables concurrent hardware and firmware editing compiling and debugging of PSoC 3 PSoC 4 PSoC 5LP PSoC 4 BLE PRoC BLE and EZ BLE module systems with no code size limitations PSoC peripherals are designed using schematic capture and simple graphical user interface GUI with over 120 pre verified production ready PSoC Components PSoC Components are analog and digital virt...

Страница 3: ...0 Serial Communication 22 Memory 23 System Resources 23 Environmental Specifications 29 Environmental Compliance 29 RF Certification 29 Safety Certification 29 Environmental Conditions 29 ESD and EMI Protection 29 Regulatory Information 30 FCC 30 Industry Canada IC Certification 31 European R TTE Declaration of Conformity 31 MIC Japan 32 KC Korea 32 Packaging 33 Ordering Information 35 Part Number...

Страница 4: ...d within the physical dimensions shown in the mechanical drawings in Figure 1 All dimensions are in millimeters mm Table 1 Module Design Dimensions See Figure 1 on page 5 for the mechanical reference drawing for CYBLE 2120XX X0 Dimension Item Specification Module dimensions Length X 14 52 0 15 mm Width Y 19 20 0 15 mm Antenna location dimensions Length X 11 00 0 15 mm Width Y 5 00 0 15 mm PCB thic...

Страница 5: ...wing Top View View from Top Bottom View Seen from Bottom Side View Note 1 No metal should be located beneath or above the antenna area Only bare PCB material should be located beneath the antenna area For more information on recommended host PCB layout see Figure 3 Figure 4 Figure 5 and Figure 6 and Table 3 ...

Страница 6: ...d at the far corner This placement minimizes the additional recommended keep out area stated in item 2 Refer to AN96841 for module placement best practices 2 To maximize RF performance the area immediately around the Cypress BLE module trace antenna should contain an additional keep out area where no grounding or signal trace are contained The keep out area applies to all layers of the host board ...

Страница 7: ...imeters unless otherwise noted Pad length of 1 27 mm 0 635 mm from center of the pad on either side shown in Figure 6 is the minimum recommended host pad length The host PCB layout pattern can be completed using either Figure 4 Figure 5 or Figure 6 It is not necessary to use all figures to complete the host PCB layout pattern Figure 4 Host Layout Pattern for CYBLE 2120XX X0 Figure 5 Module Pad Loc...

Страница 8: ... 13 6 0 39 11 23 15 35 442 13 7 0 39 12 50 15 35 492 13 8 0 39 13 77 15 35 542 13 9 0 39 15 04 15 35 592 13 10 0 39 16 31 15 35 642 13 11 0 39 17 58 15 35 692 13 12 2 04 18 82 80 31 740 94 13 3 31 18 82 130 31 740 94 14 4 58 18 82 180 31 740 94 15 5 85 18 82 230 31 740 94 16 7 12 18 82 280 31 740 94 17 8 39 18 82 330 31 740 94 18 9 66 18 82 380 31 740 94 19 10 93 18 82 430 31 740 94 20 12 20 18 82...

Страница 9: ...0_RX SCB0_MOSI SCB0_SDA TCPWM Sensor 20 P1 0 TCPWM Sensor 21 P0 4 SCB0_RX SCB0_MOSI SCB0_SDA TCPWM Sensor 22 P0 5 SCB0_TX SCB0_MISO SCB0_SCL TCPWM Sensor 23 P0 7 SCB0_CTS SCB0_SCLK TCPWM Sensor SWDCLK 24 P0 6 SCB0_RTS SCB0_SS0 TCPWM Sensor SWDIO 25 GND 5 Ground Connection 26 GND 5 Ground Connection 27 GND 5 Ground Connection 28 GND 5 Ground Connection 29 VDDR Radio Power Supply 1 9V to 5 5V 30 P5 ...

Страница 10: ...tion options are available for any application 1 Single supply Connect VDD and VDDR to the same supply 2 Independent supply Power VDD and VDDR separately External Component Recommendation In either connection scenario it is recommended to place an external ferrite bead between the supply and the module connection The ferrite bead should be positioned as close as possible to the module pin connecti...

Страница 11: ...Document Number 002 09764 Rev G Page 11 of 39 CYBLE 212019 00 CYBLE 212023 10 Figure 8 Recommended Host Schematic for an Independent Supply Option Two Ferrite Bead Option Seen from Bottom ...

Страница 12: ...Document Number 002 09764 Rev G Page 12 of 39 CYBLE 212019 00 CYBLE 212023 10 The CYBLE 2120XX X0 schematic is shown in Figure 9 Figure 9 CYBLE 2120XX X0 Schematic Diagram ...

Страница 13: ... Table 6 details trace antenna used in the CYBLE 2120XX X0 module For more information see Table 8 Table 6 Trace Antenna Specifications Component Reference Designator Description Silicon U1 56 pin QFN Programmable Radio on Chip PRoC with BLE Crystal Y1 24 000 MHz 12PF Crystal Y2 32 768 kHz 12 5PF Item Description Frequency Range 2400 2500 MHz Peak Gain 0 5 dBi typical Average Gain 0 5 dBi typical ...

Страница 14: ... IGPIO_ABS Maximum current per GPIO 25 25 mA Absolute maximum IGPIO_injection GPIO injection current Maximum for VIH VDD and minimum for VIL VSS 0 5 0 5 mA Absolute maximum current injected per pin LU Pin current for latch up 200 200 mA Parameter Description Min Typ Max Units Details Conditions RFO RF output power on ANT 18 0 3 dBm Configurable via register settings RXS RF receive sensitivity on A...

Страница 15: ...Mode VDD 1 71 V to 1 89 V Regulator Bypassed IDD19 WDT with WCO on A T 25 C IDD20 WDT with WCO on A T 40 C to 85 C Hibernate Mode VDD 1 8 V to 3 6 V IDD27 GPIO and reset active 150 nA T 25 C VDD 3 3 V IDD28 GPIO and reset active nA T 40 C to 85 C Hibernate Mode VDD 3 6 V to 5 5 V IDD29 GPIO and reset active nA T 25 C VDD 5 V IDD30 GPIO and reset active nA T 40 C to 85 C Stop Mode VDD 1 8 V to 3 6 ...

Страница 16: ...t VDD 2 7 V 2 0 V VIL Input voltage LOW threshold 0 3 VDD V CMOS input LVTTL input VDD 2 7 V 0 3 VDD V LVTTL input VDD 2 7 V 0 8 V VOH Output voltage HIGH level VDD 0 6 V IOH 4 mA at 3 3 V VDD Output voltage HIGH level VDD 0 5 V IOH 1 mA at 1 8 V VDD VOL Output voltage LOW level 0 6 V IOL 8 mA at 3 3 V VDD Output voltage LOW level 0 6 V IOL 4 mA at 1 8 V VDD Output voltage LOW level 0 4 V IOL 3 mA...

Страница 17: ... absolute value VIH VDD 10 A 25 C VDD 0 V VIH 3 0 V VOL Output voltage LOW level 0 4 V IOL 20 mA VDD 2 9 V Table 14 OVT GPIO AC Specifications P5_0 and P5_1 Only Parameter Description Min Typ Max Units Details Conditions TRISE_OVFS Output rise time in Fast Strong mode 1 5 12 ns 25 pF load 10 90 VDD 3 3 V TFALL_OVFS Output fall time in Fast Strong mode 1 5 12 ns 25 pF load 10 90 VDD 3 3 V TRISESS O...

Страница 18: ...n be accomplished only if the AMUX Buses are not being used for other funcitonality e g CapSense If the AMUX Buses are being used for other functions then the maximum number of single ended ADC channels is six Similarly if the AMUX Buses are being used for other functionality then the maximum number of differential ADC channels is three Table 19 SAR ADC AC Specifications Parameter Description Min ...

Страница 19: ... Conditions VCSD Voltage range of operation 1 71 5 5 V IDAC1 DNL for 8 bit resolution 1 1 LSB IDAC1 INL for 8 bit resolution 3 3 LSB IDAC2 DNL for 7 bit resolution 1 1 LSB IDAC2 INL for 7 bit resolution 3 3 LSB SNR Ratio of counts of finger to noise 5 Ratio Capacitance range of 9 pF to 35 pF 0 1 pF sensitivity Radio is not operating during the scan IDAC1_CRT1 Output current of IDAC1 8 bits in High...

Страница 20: ... ns TTENWIDEXT Enable pulse width external 2 TCLK ns TTIMRESWINT Reset pulse width internal 2 TCLK ns TTIMRESEXT Reset pulse width external 2 TCLK ns Table 22 Counter DC Specifications Parameter Description Min Typ Max Units Details Conditions ICTR1 Block current consumption at 3 MHz 42 A 16 bit counter ICTR2 Block current consumption at 12 MHz 130 A 16 bit counter ICTR3 Block current consumption ...

Страница 21: ...TCLK ns TPWMKILLEXT Kill pulse width external 2 TCLK ns TPWMEINT Enable pulse width internal 2 TCLK ns TPWMENEXT Enable pulse width external 2 TCLK ns TPWMRESWINT Reset pulse width internal 2 TCLK ns TPWMRESWEXT Reset pulse width external 2 TCLK ns Table 26 LCD Direct Drive DC Specifications Parameter Description Min Typ Max Units Details Conditions ILCDLOW Operating current in low power mode 17 5...

Страница 22: ... Description Min Typ Max Units Details Conditions ISPI1 Block current consumption at 1 Mbps 360 A ISPI2 Block current consumption at 4 Mbps 560 A ISPI3 Block current consumption at 8 Mbps 600 A Table 33 Fixed SPI AC Specifications Parameter Description Min Typ Max Units Details Conditions FSPI SPI operating frequency master 6x over sampling 8 MHz Table 34 Fixed SPI Master Mode AC Specifications Pa...

Страница 23: ...TA 85 C 10 K P E cycles 10 years Table 38 POR DC Specifications Parameter Description Min Typ Max Units Details Conditions VRISEIPOR Rising trip voltage 0 80 1 45 V VFALLIPOR Falling trip voltage 0 75 1 40 V VIPORHYST Hysteresis 15 200 mV Table 39 POR AC Specifications Parameter Description Min Typ Max Units Details Conditions TPPOR_TR Precision power on reset PPOR response time in Active and Slee...

Страница 24: ...SEL 3 0 1001b 2 54 2 60 2 67 V VLVI11 LVI_A D_SEL 3 0 1010b 2 63 2 70 2 77 V VLVI12 LVI_A D_SEL 3 0 1011b 2 73 2 80 2 87 V VLVI13 LVI_A D_SEL 3 0 1100b 2 83 2 90 2 97 V VLVI14 LVI_A D_SEL 3 0 1101b 2 93 3 00 3 08 V VLVI15 LVI_A D_SEL 3 0 1110b 3 12 3 20 3 28 V VLVI16 LVI_A D_SEL 3 0 1111b 4 39 4 50 4 61 V LVI_IDD Block current 100 A Table 43 Voltage Monitor AC Specifications Parameter Description ...

Страница 25: ...at 32 kHz 0 3 1 05 A Table 48 ILO AC Specifications Parameter Description Min Typ Max Units Details Conditions TSTARTILO1 ILO startup time 2 ms FILOTRIM1 32 kHz trimmed frequency 15 32 50 kHz Parameter Description Value Details Conditions ECOTRIM 24 MHz trim value firmware configuration 0x0000BCBC Recommended trim value that needs to be loaded to register CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG Table ...

Страница 26: ...LE CA 04 C OBB3 Out of band blocking Wanted signal at 67 dBm and Interferer at F 2484 2997 MHz 35 27 dBm RF PHY Specification RCV LE CA 04 C OBB4 Out of band blocking Wanted signal a 67 dBm and Interferer at F 3000 12750 MHz 30 27 dBm RF PHY Specification RCV LE CA 04 C IMD Inter modulation performance Wanted signal at 64 dBm and 1 Mbps BLE third fourth and fifth offset channel 50 dBm RF PHY Speci...

Страница 27: ...rrent in normal mode 16 4 mA Measured at VDDR IRX HIGHGAIN Receive current in high gain mode 21 5 mA ITX 3dBm TX current at 3 dBm setting PA10 20 mA ITX 0dBm TX current at 0 dBm setting PA7 16 5 mA ITX_RF 0dBm Radio TX current at 0 dBm setting PA7 15 6 mA Measured at VDDR ITX_RF 0dBm Radio TX current at 0 dBm excluding Balun loss 14 2 mA Guaranteed by design simulation ITX 3dBm TX current at 3 dBm...

Страница 28: ...DLE to BLE TX transition time 120 140 s IDLE2RX BLE IDLE to BLE RX transition time 75 120 s RSSI Specifications RSSI ACC RSSI accuracy 5 dB RSSI RES RSSI resolution 1 dB RSSI PER RSSI sample period 6 s Table 50 BLE Subsystem continued Parameter Description Min Typ Max Units Details Conditions ...

Страница 29: ...he Cypress BLE module Table 51 Environmental Conditions for CYBLE 2120XX X0 ESD and EMI Protection Exposed components require special attention to ESD and electromagnetic interference EMI A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD pr...

Страница 30: ... circuit different from that to which the receiver is connected Consult the dealer or an experienced radio TV technician for help LABELING REQUIREMENTS The Original Equipment Manufacturer OEM must ensure that FCC labelling requirements are met This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product a...

Страница 31: ... 1 this device may not cause interference and 2 this device must accept any interference including interference that may cause undesired operation of the device Le présent appareil est conforme aux CNR d Industrie Canada applicables aux appareils radio exempts de licence L exploitation est autorisée aux deux conditions suivantes 1 l appareil ne doit pas produire de brouillage et 2 l utilisateur de...

Страница 32: ...dule with type certification number 203 JN0509 End products that integrate CYBLE 212023 10 do not need additional MIC Japan certification for the end product End product can display the certification label of the embedded module KC Korea CYBLE 212019 00 is certified for use in Korea with certificate number MSIP CRM Cyp 2011 ...

Страница 33: ...ils the orientation of the CYBLE 2120XX X0 in the tape as well as the direction for unreeling Figure 11 Component Orientation in Tape and Unreeling Direction Table 52 Solder Reflow Peak Temperature Module Part Number Package Maximum Peak Temperature Maximum Time at Peak Temperature No of Cycles CYBLE 2120XX X0 31 pad SMT 260 C 30 seconds 2 Table 53 Package Moisture Sensitivity Level MSL IPC JEDEC ...

Страница 34: ...el dimensions used for the CYBLE 212019 00 Figure 12 Reel Dimensions The CYBLE 2120XX X0 is designed to be used with pick and place equipment in an SMT manufacturing environment The center of mass for the CYBLE 2120XX X0 is detailed in Figure 13 Figure 13 CYBLE 2120XX X0 Center of Mass Seen from Top ...

Страница 35: ...ss sales representative To locate the nearest Cypress office visit our website Table 54 Ordering Information Part Number CPU Speed MHz Flash Size KB CapSense SCB TCPWM 12 Bit SAR ADC I2 S LCD Package Packing Certified CYBLE 212019 00 48 256 Yes 2 4 1 Msps Yes Yes 31 SMT Tape and Reel Yes CYBLE 212023 10 48 256 Yes 2 4 1 Msps Yes Yes 31 SMT Tape and Reel No Table 55 Tape and Reel Package Quantity a...

Страница 36: ...ustry Canada IDE integrated design environment KC Korea Certification MIC Ministry of Internal Affairs and Communications Japan PCB printed circuit board RX receive QDID qualification design ID SMT surface mount technology a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBs TCPWM timer counter pulse width modulator PWM TUV Germany Techni...

Страница 37: ...Updated Power Consumption Replaced Stop 60 nA with XRES wakeup with Stop 60 nA with GPIO P2 2 or XRES wakeup under Low power mode support Updated More Information Added additional Knowledge Base Article references Updated Electrical Specification Updated System Resources Updated Internal Low Speed Oscillator Updated Table 49 Updated details in Value column corresponding to ECOTRIM parameter Update...

Страница 38: ...age 38 of 39 CYBLE 212019 00 CYBLE 212023 10 G 6002363 DSO 12 22 2017 Updated reel dimensions in Figure 10 and Figure 12 Document History Page Document Title CYBLE 212019 00 CYBLE 212023 10 EZ BLE PRoC Module Document Number 002 09764 ...

Страница 39: ... assume any liability arising out of the application or use of any product or circuit described in this document Any information provided in this document including any sample design information or programming code is provided only for reference purposes It is the responsibility of the user of this document to properly design program and test the functionality and safety of any application made of...

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