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May 2004

© Cypress MicroSystems, Inc. 2003 — Document No. 38-12009 Rev. *E

10

2.

Register Reference

This chapter lists the registers of the CY8C22x13 PSoC device by way of mapping tables, in offset order. For detailed register infor-
mation, reference the PSoC™ Mixed Signal Array Technical Reference Manual.

2.1

Register Conventions

2.1.1

Abbreviations Used

The register conventions specific to this section are listed in the
following table.

2.2

Register Mapping Tables

The PSoC device has a total register address space of 512
bytes. The register space is also referred to as IO space and is
broken into two parts. The XOI bit in the Flag register deter-
mines which bank the user is currently in. When the XOI bit is
set, the user is said to be in the “extended” address space or
the “configuration” registers.

Note In the following register mapping tables, blank fields are
Reserved and should not be accessed.

Convention

Description

RW

Read and write register or bit(s)

R

Read register or bit(s)

W

Write register or bit(s)

L

Logical register or bit(s)

C

Clearable register or bit(s)

#

Access is bit specific

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Содержание CY8C22113

Страница 1: ...SoC Blocks 3 Rail to Rail Analog PSoC Blocks Provide Up to 14 Bit ADCs Up to 9 Bit DACs Programmable Gain Amplifiers Programmable Filters and Comparators 4 Digital PSoC Blocks Provide 8 to 32 Bit Timers Counters and PWMs CRC and PRS Modules Full Duplex UART SPI Masters or Slaves Connectable to all GPIO Pins Complex Peripherals by Combining Blocks Precision Programmable Clocking Internal 2 5 24 48 ...

Страница 2: ...peripheral configurations include those listed below PWMs 8 to 32 bit PWMs with Dead band 8 to 32 bit Counters 8 to 32 bit Timers 8 to 32 bit UART 8 bit with selectable parity up to 1 SPI master and slave up to 1 I2C slave and master 1 available as a System Resource Cyclical Redundancy Checker Generator 8 to 32 bit IrDA up to 1 Pseudo Random Sequence Generators 8 to 32 bit The digital blocks can b...

Страница 3: ...ADCs The I2C module provides 100 and 400 kHz communication over two wires Slave master and multi master modes are all supported Low Voltage Detection LVD interrupts can signal the appli cation of falling voltage levels while the advanced POR Power On Reset circuit eliminates the need for a system supervisor An internal 1 3 voltage reference provides an absolute refer ence for the analog system inc...

Страница 4: ... everything from technical assistance to completed PSoC designs To contact or become a PSoC Consultant go to the following Cypress support web site http www cypress com support cypros cfm Technical Support PSoC application engineers take pride in fast and accurate response They can be reached with a 4 hour guaranteed response at http www cypress com support login cfm Application Notes A long list ...

Страница 5: ...use absolute addressing or can be compiled in relative mode and linked with other software modules to get absolute addressing C Language Compiler A C language compiler is available that supports Cypress MicroSystems PSoC family devices Even if you have never worked in the C language before the product quickly allows you to create complete C programs for the PSoC family devices The embedded optimiz...

Страница 6: ...d by the user module The development process starts when you open a new project and bring up the Device Editor a pictorial environment GUI for configuring the hardware You pick the user modules you need for your project and map them onto the PSoC blocks with point and click simplicity Next you build signal chains by intercon necting user modules to each other and the IO pins At this stage you also...

Страница 7: ...ifications 15 3 3 3 DC Operational Amplifier Specifications 16 3 3 4 DC Analog Output Buffer Specifications 18 3 3 5 DC Analog Reference Specifications 19 3 3 6 DC Analog PSoC Block Specifications 19 3 3 7 DC POR and LVD Specifications 20 3 3 8 DC Programming Specifications 21 3 4 AC Electrical Characteristics 22 3 4 1 AC Chip Level Specifications 22 3 4 2 AC General Purpose IO Specifications 24 3...

Страница 8: ... No Type Pin Name Description CY8C22213 20 Pin PSoC Device Digital Analog 1 IO I P0 7 Analog column mux input 2 IO IO P0 5 Analog column mux input and column output 3 IO I P0 3 Analog column mux input 4 IO I P0 1 Analog column mux input 5 Power Vss Ground connection 6 IO P1 7 I2C Serial Clock SCL 7 IO P1 5 I2C Serial Data SDA 8 IO P1 3 9 IO P1 1 Crystal Input XTALin I2C Serial Clock SCL 10 Power V...

Страница 9: ...set with internal pull down 19 NC No connection Do not use 20 NC No connection Do not use 21 NC No connection Do not use 22 NC No connection Do not use 23 IO I P0 0 Analog column mux input 24 IO I P0 2 Analog column mux input 25 NC No connection Do not use 26 IO I P0 4 Analog column mux input 27 IO I P0 6 Analog column mux input 28 Power Vdd Supply voltage 29 IO I P0 7 Analog column mux input 30 I...

Страница 10: ...pping Tables The PSoC device has a total register address space of 512 bytes The register space is also referred to as IO space and is broken into two parts The XOI bit in the Flag register deter mines which bank the user is currently in When the XOI bit is set the user is said to be in the extended address space or the configuration registers Note In the following register mapping tables blank fi...

Страница 11: ...B RW 1C 5C 9C DC 1D 5D 9D INT_CLR3 DD RW 1E 5E 9E INT_MSK3 DE RW 1F 5F 9F DF DBB00DR0 20 AMX_IN 60 RW A0 INT_MSK0 E0 RW DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW DBB00DR2 22 RW 62 A2 INT_VC E2 RC DBB00CR0 23 ARF_CR 63 RW A3 RES_WDT E3 W DBB01DR0 24 CMP_CR0 64 A4 DEC_DH E4 RC DBB01DR1 25 W ASY_CR 65 A5 DEC_DL E5 RC DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW DBB01CR0 27 67 A7 DEC_CR1 E7 RW DCB02DR0 28 6...

Страница 12: ... 5B 9B DB 1C 5C 9C DC 1D 5D 9D OSC_GO_EN DD RW 1E 5E 9E OSC_CR4 DE RW 1F 5F 9F OSC_CR3 DF RW DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW 23 63 A3 VLT_CR E3 RW DBB01FN 24 RW 64 A4 VLT_CMP E4 R DBB01IN 25 RW 65 A5 E5 DBB01OU 26 RW AMD_CR1 66 RW A6 E6 27 ALT_CR0 67 RW A7 E7 DCB02FN 28 RW 68 A8 IMO_TR E8 W DCB02...

Страница 13: ...following table lists the units of measure that are used in this chapter 5 25 4 75 3 00 93 kHz 12 MHz 24 MHz CPU Frequency Vdd Voltage V a l i d O p e r a t i n g R e g i o n Table 3 1 Units of Measure Symbol Unit of Measure Symbol Unit of Measure oC degree Celsius µW micro watts dB decibels mA milli ampere fF femto farad ms milli second Hz hertz mV milli volts KB 1024 bytes nA nano ampere Kbit 10...

Страница 14: ... to Vss 0 5 6 0 V VIO DC Input Voltage Vss 0 5 Vdd 0 5 V DC Voltage Applied to Tri state Vss 0 5 Vdd 0 5 V IMIO Maximum Current into any Port Pin 25 50 mA IMAIO Maximum Current into any Port Pin Configured as Analog Driver 50 50 mA Static Discharge Voltage 2000 V Latch up Current 200 mA Table 3 3 Operating Temperature Symbol Description Min Typ Max Units Notes TA Ambient Temperature 40 85 oC TJ Ju...

Страница 15: ...ep Time needed for reliable system operation This should be compared with devices that have similar functions enabled 3 6 5 µA Conditions are with internal slow speed oscilla tor Vdd 3 3V 40 oC TA 55 oC ISBH Sleep Mode Current with POR LVD Sleep Timer and WDT at high temperature a 4 25 µA Conditions are with internal slow speed oscilla tor Vdd 3 3V 55 o C TA 85 o C ISBXTL Sleep Mode Current with P...

Страница 16: ...e Input Offset Voltage Drift 7 0 35 0 µV oC IEBOA Input Leakage Current Port 0 Analog Pins 20 pA Gross tested to 1 µA CINOA Input Capacitance Port 0 Analog Pins 4 5 9 5 pF Package and pin dependent Temp 25oC VCMOA Common Mode Voltage Range Common Mode Voltage Range high power or high opamp bias 0 0 Vdd Vdd 0 5 V The common mode input voltage range is mea sured through an analog output buffer The s...

Страница 17: ... through an analog output buffer The specification includes the limitations imposed by the characteristics of the analog output buffer GOLOA Open Loop Gain Power Low Power Medium Power High 60 60 80 dB Specification is applicable at high power For all other bias modes except high power high opamp bias minimum is 60 dB VOHIGHOA High Output Voltage Swing worst case internal load Power Low Power Medi...

Страница 18: ...oad 32 ohms to Vdd 2 Power Low Power High 0 5 x Vdd 1 1 0 5 x Vdd 1 1 V V VOLOWOB Low Output Voltage Swing Load 32 ohms to Vdd 2 Power Low Power High 0 5 x Vdd 1 3 0 5 x Vdd 1 3 V V ISOB Supply Current Including Bias Cell No Load Power Low Power High 1 1 2 6 5 1 8 8 mA mA PSRROB Supply Voltage Rejection Ratio 60 dB Table 3 9 3 3V DC Analog Output Buffer Specifications Symbol Description Min Typ Ma...

Страница 19: ...PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C TA 85 C or 3 0V to 3 6V and 40 C TA 85 C respectively Typical parameters apply to 5V and 3 3V at 25 C and are for design guidance only or unless otherwise specified Table 3 10 5V DC Analog Reference Specifications Symbol Description Min Ty...

Страница 20: ...bol Description Min Typ Max Units Notes VPPOR0R VPPOR1R VPPOR2R Vdd Value for PPOR Trip positive ramp PORLEV 1 0 00b PORLEV 1 0 01b PORLEV 1 0 10b 2 908 4 394 4 548 V V V VPPOR0 VPPOR1 VPPOR2 Vdd Value for PPOR Trip negative ramp PORLEV 1 0 00b PORLEV 1 0 01b PORLEV 1 0 10b 2 816 4 394 4 548 V V V VPH0 VPH1 VPH2 PPOR Hysteresis PORLEV 1 0 00b PORLEV 1 0 01b PORLEV 1 0 10b 92 0 0 mV mV mV VLVD0 VLV...

Страница 21: ...Applying Vihp to P1 0 or P1 1 During Programming or Verify 1 5 mA Driving internal pull down resistor VOLV Output Low Voltage During Programming or Verify Vss 0 75 V VOHV Output High Voltage During Programming or Verify Vdd 1 0 Vdd V FlashENPB Flash Endurance per block 50 000 Erase write cycles per block FlashENT Flash Endurance total a a A maximum of 36 x 50 000 block endurance cycles is allowed ...

Страница 22: ... data sheets for information on maximum frequencies for user modules MHz Refer to the AC Digital Block Specifications below F24M Digital PSoC Block Frequency 0 24 24 6b e d e 3 0V 5 25V MHz F32K1 Internal Low Speed Oscillator Frequency 15 32 64 kHz F32K2 External Crystal Oscillator 32 768 kHz Accuracy is capacitor and crystal dependent 50 duty cycle FPLL PLL Frequency 23 986 MHz Is a multiple x732...

Страница 23: ...k for Low Gain Setting Timing Diagram Figure 3 4 External Crystal Oscillator Startup Timing Diagram Figure 3 5 24 MHz Period Jitter IMO Timing Diagram Figure 3 6 32 kHz Period Jitter ECO Timing Diagram 24 MHz FPLL PLL Enable TPLLSLEWLOW PLL Gain 1 32 kHz F32K2 32K Select TOS Jitter24M1 F24M Jitter32k F32K2 Feedback ...

Страница 24: ... C and are for design guidance only or unless otherwise specified Figure 3 7 GPIO Timing Diagram Table 3 16 AC GPIO Specifications Symbol Description Min Typ Max Units Notes FGPIO GPIO Operating Frequency 0 12 MHz TRiseF Rise Time Normal Strong Mode Cload 50 pF 3 18 ns Vdd 4 5 to 5 25V 10 90 TFallF Fall Time Normal Strong Mode Cload 50 pF 2 18 ns Vdd 4 5 to 5 25V 10 90 TRiseS Rise Time Slow Strong...

Страница 25: ... High Power High Power High Opamp Bias High 5 9 0 92 0 72 µs µs µs µs µs µs Specification maximums for low power and high opamp bias medium power and medium power and high opamp bias levels are between low and high power levels SRROA Rising Slew Rate 20 to 80 10 pF load Unity Gain Power Low Power Low Opamp Bias High Power Medium Power Medium Opamp Bias High Power High Power High Opamp Bias High 0 ...

Страница 26: ...oad Unity Gain Power Low Power Low Opamp Bias High Power Medium Power Medium Opamp Bias High Power High 3 3 Volt High Bias Operation not supported Power High Opamp Bias High 3 3 Volt High Power High Opamp Bias not supported 0 31 2 7 V µs V µs V µs V µs V µs V µs Specification minimums for low power and high opamp bias medium power and medium power and high opamp bias levels are between low and hig...

Страница 27: ...nizers running at 24 MHz 42 ns nominal period ns Maximum Frequency No Capture 49 2 MHz 4 75V Vdd 5 25V Maximum Frequency With Capture 24 6 MHz Counter Enable Pulse Width 50a ns Maximum Frequency No Enable Input 49 2 MHz 4 75V Vdd 5 25V Maximum Frequency Enable Input 24 6 MHz Dead Band Kill Pulse Width Asynchronous Restart Mode 20 ns Synchronous Restart Mode 50a ns Disable Mode 50a ns Maximum Frequ...

Страница 28: ...F Load Power Low Power High 0 65 0 65 V µs V µs SRFOB Falling Slew Rate 80 to 20 1V Step 100pF Load Power Low Power High 0 65 0 65 V µs V µs BWOB Small Signal Bandwidth 20mVpp 3dB BW 100pF Load Power Low Power High 0 8 0 8 MHz MHz BWOB Large Signal Bandwidth 1Vpp 3dB BW 100pF Load Power Low Power High 300 300 kHz kHz Table 3 21 3 3V AC Analog Output Buffer Specifications Symbol Description Min Typ...

Страница 29: ...h 150 µs Table 3 23 3 3V AC External Clock Specifications Symbol Description Min Typ Max Units Notes FOSCEXT Frequency with CPU Clock divide by 1a a Maximum CPU frequency is 12 MHz at 3 3V With the CPU clock divider set to 1 the external clock must adhere to the maximum frequency and duty cycle requirements 0 12 12 MHz FOSCEXT Frequency with CPU Clock divide by 2 or greaterb b If the frequency of ...

Страница 30: ... LOW Period of the SCL Clock 4 7 1 3 µs THIGHI2C HIGH Period of the SCL Clock 4 0 0 6 µs TSUSTAI2C Set up Time for a Repeated START Condition 4 7 0 6 µs THDDATI2C Data Hold Time 0 0 µs TSUDATI2C Data Set up Time 250 100a a A Fast Mode I2C bus device can be used in a Standard Mode I2C bus system but the requirement tSU DAT 250 ns must then be met This will automatically be the case if the device do...

Страница 31: ...ing Information This chapter illustrates the packaging specifications for the CY8C22x13 PSoC device along with the thermal impedances for each package and the typical package capacitance on crystal pins 4 1 Packaging Dimensions Figure 4 1 8 Lead 300 Mil PDIP 51 85075 A Feedback ...

Страница 32: ...Document No 38 12009 Rev E 32 CY8C22x13 Final Data Sheet 4 Packaging Information Figure 4 2 8 Lead 150 Mil SOIC Figure 4 3 20 Lead 300 Mil Molded DIP 51 85066 B 51 85066 B 51 85066 C 51 85011 A 51 85011 A Feedback ...

Страница 33: ...June 3 2004 Document No 38 12009 Rev E 33 CY8C22x13 Final Data Sheet 4 Packaging Information Figure 4 4 20 Lead 210 Mil SSOP Figure 4 5 20 Lead 300 Mil Molded SOIC 51 85077 C 51 85024 B Feedback ...

Страница 34: ...le 4 1 Thermal Impedances per Package Package Typical θJA 8 PDIP 123 oC W 8 SOIC 185 oC W 20 PDIP 109 oC W 20 SSOP 117 o C W 20 SOIC 81 oC W 32 MLF 22 oC W TJ TA POWER x θJA Table 4 2 Typical Package Capacitance on Crystal Pins Package Package Capacitance 8 PDIP 2 8 pF 8 SOIC 2 0 pF 20 PDIP 3 0 pF 20 SSOP 2 6 pF 20 SOIC 2 5 pF 32 MLF 2 0 pF 51 85188 32 X 138 MIL Y 138 MIL Feedback ...

Страница 35: ...4 1 No 8 Pin 150 Mil SOIC Tape and Reel CY8C22113 24SIT 2 256 No 40C to 85C 4 3 6 4 1 No 20 Pin 300 Mil DIP CY8C22213 24PI 2 256 No 40C to 85C 4 3 16 8 1 Yes 20 Pin 210 Mil SSOP CY8C22213 24PVI 2 256 No 40C to 85C 4 3 16 8 1 Yes 20 Pin 210 Mil SSOP Tape and Reel CY8C22213 24PVIT 2 256 No 40C to 85C 4 3 16 8 1 Yes 20 Pin 300 Mil SOIC CY8C22213 24SI 2 256 No 40C to 85C 4 3 16 8 1 Yes 20 Pin 300 Mil ...

Страница 36: ...ress Micro Systems against all charges Cypress MicroSystems products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress MicroSystems 2700 162nd Street SW Building D Lynnwood WA 98037 Phone 800 669 0557 Facsimile 425 787 4641 Web Sites Company Information http www cypress...

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