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CY7C68053

Document # 001-06120 Rev *F

Page 31 of 39

9.9

Slave FIFO Output Enable 

9.10

Slave FIFO Address to Flags/Data 

Table 9-12.  Slave FIFO Output Enable Parameters

Parameter

Description

Min.

Max.

Unit

t

OEon

SLOE Assert to FIFO DATA Output

10.5

ns

t

OEoff

SLOE Deassert to FIFO DATA Hold

2.15

10.5

ns

Table 9-13.  Slave FIFO Address to Flags/Data Parameters

Parameter

Description

Min.

Max.

Unit

t

XFLG

FIFOADR[1:0] to FLAGS Output Propagation Delay

10.7

ns

t

XFD

FIFOADR[1:0] to FIFODATA Output Propagation Delay

14.3

ns

SLOE

DATA

t

OEon

t

OEoff

Figure 9-9. Slave FIFO Output Enable Timing Diagram

[17]

FIFOADR [1.0]

DATA

t

XFLG

t

XFD

FLAGS

N

N+1

Figure 9-10. Slave FIFO Address to Flags/Data Timing Diagram

[17]

[+] Feedback 

Содержание MoBL-USB CY7C68053

Страница 1: ...ocks per instruction cycle Three counter timers Expanded interrupt system Two data pointers 1 8V core operation 1 8V 3 3V IO operation Vectored USB interrupts and GPIF FIFO interrupts Separate data bu...

Страница 2: ...s and documentation For more infor mation visit http www cypress com 3 0 Functional Overview The functionality of this chip is described in the sections below 3 1 USB Signaling Speed FX2LP18 operates...

Страница 3: ...t the firmware sets DISCON to 1 To reconnect the firmware clears DISCON to 0 Before reconnecting the firmware sets or clears the RENUM bit to indicate whether the firmware or the Default USB Device ha...

Страница 4: ...h speed operation 7 18 EP0ACK FX2LP18 ACK d the CONTROL Handshake 8 1C Reserved 9 20 EP0 IN EP0 IN ready to be loaded with data 10 24 EP0 OUT EP0 OUT has USB data 11 28 EP1 IN EP1 IN ready to be loade...

Страница 5: ...3 WU2 pin The second wakeup pin WU2 can also be configured as a general purpose IO pin This allows a simple external R C network to be used as a periodic wakeup source Note that WAKEUP is by default a...

Страница 6: ...ochronous EP4 and EP8 can be double buffered while EP2 and 6 can be double triple or quad buffered For high speed endpoint configuration options see Figure 3 5 3 12 3 Set up Data Buffer A separate 8 b...

Страница 7: ...N EP1 OUT Figure 3 5 Endpoint Configuration 1024 1024 EP6 1024 512 512 EP8 512 512 EP6 512 512 512 512 EP2 512 512 EP4 512 512 EP2 512 512 EP4 512 512 EP2 512 512 EP4 512 512 EP2 512 512 512 512 EP2 5...

Страница 8: ...clock with the IFCLKSRC bit Each endpoint can individually be selected for byte or word operation by an internal configuration bit and a Slave FIFO Output Enable signal SLOE enables data of the selec...

Страница 9: ...The core has the ability to directly edit the data contents of the internal 16 kByte RAM and of the internal 512 byte scratch pad RAM via a vendor specific command This capability is normally used whe...

Страница 10: ...he signals on the right edge of the diagram The 8051 selects the interface mode using the IFCONFIG 1 0 register bits Port mode is the power on default configuration Table 3 6 Strap Boot EEPROM Address...

Страница 11: ...2 CY7C68053 56 pin VFBGA Pin Assignment Top view 1 2 3 4 5 6 7 8 A B C D E F G H 1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B 1C 2C 3C 4C 5C 6C 7C 8C 1D 2D 7D 8D 1E 2E 7E 8E 1F 2F 3F 4F 5F 6F 7F 8F...

Страница 12: ...other clock source 2C XTALOUT Output N A Crystal Output Connect this signal to a 24 MHz parallel resonant funda mental mode crystal and load capacitor to GND If an external clock is used to drive XTAL...

Страница 13: ...bus 4F PB1 or FD 1 I O Z I PB1 Multiplexed pin whose function is selected by the following bits IFCONFIG 1 0 PB1 is a bidirectional IO port pin FD 1 is the bidirectional FIFO GPIF data bus 4H PB2 or F...

Страница 14: ...ted by the IFCONFIG 1 0 and EPxFIFOCFG 0 wordwide bits FD 15 is the bidirectional FIFO GPIF data bus 1A RDY0 or SLRD Input N A Multiplexed pin whose function is selected by the following bits IFCONFIG...

Страница 15: ...quired 3G SDA OD Z Data for the I2 C interface Connect to VCC_IO or VCC with a 2 2K 10K pull up resistor An I2 C peripheral is required 5A VCC_IO Power N A VCC Connect this pin to 1 8V to 3 3V power s...

Страница 16: ...0 TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr E612 1 EP2CFG Endpoint 2 Configuration VALID DIR TYPE1 TYPE0 SIZE 0 BUF1 BUF0 10100010 bbbbbrbb E613 1 EP4CFG Endpoint 4 Configuration VALID DIR TYPE1 TYPE0 0...

Страница 17: ...slave FIFO Programmable Flag H DECIS PKTSTAT 0 OUT PFC10 OUT PFC9 0 0 PFC8 00001000 bbrbbrrb E637 H S 1 EP8FIFOPFL 10 Endpoint 8 slave FIFO Programmable Flag L PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0...

Страница 18: ...CRC5 CRC4 CRC3 CRC2 CRC1 CRC0 10111010 RW E67F 1 UDMACRC QUALIFIER UDMA CRC Qualifier QENABLE 0 0 0 QSTATE QSIGNAL2 QSIGNAL1 QSIGNAL0 00000000 brrrbbbb USB CONTROL E680 1 USBCS USB Control Status HSM...

Страница 19: ...Data Pointer high address byte A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW E6B4 1 SUDPTRL Set up Data Pointer low address byte A7 A6 A5 A4 A3 A2 A1 0 xxxxxxx0 bbbbbbbr E6B5 1 SUDPTRCTL Set up Data Point...

Страница 20: ...x x x x x x x xxxxxxxx W 3 Reserved E6F0 1 XGPIFSGLDATH GPIF Data H 16 bit mode only D15 D14 D13 D12 D11 D10 D9 D8 xxxxxxxx RW E6F1 1 XGPIFSGLDATLX Read Write GPIF Data L trigger transaction D7 D6 D5...

Страница 21: ...upt 2 clear x x x x x x x x xxxxxxxx W A2 1 Reserved x x x x x x x x xxxxxxxx W A3 5 Reserved A8 1 IE Interrupt Enable bit addressable EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 00000000 RW A9 1 Reserved AA 1 EP2...

Страница 22: ...d D8 1 EICON 12 External Interrupt Control SMOD1 1 ERESI RESI INT6 0 0 0 01000000 RW D9 7 Reserved E0 1 ACC Accumulator bit address able D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW E1 7 Reserved E8 1 EIE 12 E...

Страница 23: ...e SCL and SDA pins which are 3 3V tolerant DC Voltage Applied to Outputs in High Z State 0 5V to VCC 0 5V Maximum Power Dissipation From AVcc Supply 90 mW From IO Supply 36 mW From Core Supply 95 mW S...

Страница 24: ...Voltage HIGH IOUT 4 mA VCC_IO 0 4 V VOL Output LOW Voltage IOUT 4 mA 0 4 V IOH Output Current HIGH 4 mA IOL Output Current LOW 4 mA CIN Input Pin Capacitance Except D D 10 pF D D 15 pF ISUSP Suspend...

Страница 25: ...Clock Set up Time 9 2 ns tDAH GPIF Data Hold Time 0 ns tXGD Clock to GPIF Data Output Propagation Delay 11 ns tXCTL Clock to CTLX Output Propagation Delay 6 7 ns Notes 17 Dashed lines denote signals w...

Страница 26: ...E Turn on to FIFO Data Valid 10 5 ns tOEoff SLOE Turn off to FIFO Data Hold 2 15 10 5 ns tXFLG Clock to FLAGS Output Propagation Delay 9 5 ns tXFD Clock to FIFO Data Output Propagation Delay 11 ns Tab...

Страница 27: ...ronous parameter values use internal IFCLK setting at 48 MHz Table 9 5 Slave FIFO Asynchronous Read Parameters 20 Parameter Description Min Max Unit tRDpwl SLRD Pulse Width LOW 50 ns tRDpwh SLRD Pulse...

Страница 28: ...ck Set up Time 18 1 ns tWRH Clock to SLWR Hold Time 0 ns tSFD FIFO Data to Clock Set up Time 10 64 ns tFDH Clock to FIFO Data Hold Time 0 ns tXFLG Clock to FLAGS Output Propagation Time 9 5 ns Table 9...

Страница 29: ...opagation Delay 70 ns FLAGS tXFLG IFCLK PKTEND tSPE tPEH Figure 9 6 Slave FIFO Synchronous Packet End Strobe Timing Diagram 17 Table 9 9 Slave FIFO Synchronous Packet End Strobe Parameters with Intern...

Страница 30: ...e 9 7 shows this scenario X is the value the AUTOINLEN register is set to when the IN endpoint is configured to be in auto mode Figure 9 7 shows a scenario where two packets are being committed The fi...

Страница 31: ...ff SLOE Deassert to FIFO DATA Hold 2 15 10 5 ns Table 9 13 Slave FIFO Address to Flags Data Parameters Parameter Description Min Max Unit tXFLG FIFOADR 1 0 to FLAGS Output Propagation Delay 10 7 ns tX...

Страница 32: ...1 0 to Clock Set up Time 25 ns tFAH Clock to FIFOADR 1 0 Hold Time 10 ns Slave FIFO Asynchronous Address Parameters 20 Parameter Description Min Max Unit tSFA FIFOADR 1 0 to SLRD SLWR PKTEND Set up T...

Страница 33: ...ead condition The FIFO pointer is updated on the rising edge of the IFCLK while SLRD is asserted This starts the propagation of data from the newly addressed location to the data bus After a propagati...

Страница 34: ...ated on each rising edge of IFCLK In Figure 9 15 once the four bytes are written to the FIFO SLWR is deasserted The short 4 byte packet can be committed to the host by asserting the PKTEND signal Ther...

Страница 35: ...ivating edge of SLRD In Figure 9 16 data N is the first valid data read from the FIFO For data toappearonthe databusduringthe read cycle forexample SLRD is asserted SLOE MUST be in an asserted state S...

Страница 36: ...so updated after tXFLG from the deasserting edge of SLWR The same sequence of events is shown for a burst write and is indicated by the timing marks of T 0 through 5 Note In the burst write mode once...

Страница 37: ...8051 Address Data Busses CY7C68053 56BAXI 56 VFBGA Lead Free 16K 24 Development Tool Kit CY3687 MoBL USB FX2LP18 Development Kit TOP VIEW PIN A1 CORNER 0 50 3 50 5 00 0 10 BOTTOM VIEW 0 10 4X 3 50 5 0...

Страница 38: ...rd is required to maintain signal quality Specify impedance targets ask your board vendor what they can achieve To control impedance maintain trace widths and trace spac ing to within specifications M...

Страница 39: ...10 B 465471 See ECN OSG Changed the recommendation for the pull up resistors on I2 C Split Icc into 4 different values corresponding to the different voltage supplies Changed Isus typical to 20uA and...

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