Cypress Semiconductor MoBL-USB CY7C68053, Техническое описание, Страница: 25 / 39

CY7C68053
Document # 001-06120 Rev *F Page 25 of 39
9.0 AC Electrical Characteristics
9.1 USB Transceiver
USB 2.0-compliant in full- and high-speed modes.
9.2 GPIF Synchronous Signals
8
DATA(output)
t
XGD
IFCLK
RDY
X
DATA(input)
valid
t
SRY
t
RYH
t
IFCLK
t
SGD
CTL
X
t
XCTL
t
DAH
N N+1
GPIFADR[8:0]
t
SGA
Figure 9-1. GPIF Synchronous Signals Timing Diagram
[17]
Table 9-1. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK
[17,18]
Parameter Description Min. Max. Unit
t
IFCLK
IFCLK Period 20.83 ns
t
SRY
RDY
X
to Clock Set-up Time 8.9 ns
t
RYH
Clock to RDY
X
0 ns
t
SGD
GPIF Data to Clock Set-up Time 9.2 ns
t
DAH
GPIF Data Hold Time 0 ns
t
XGD
Clock to GPIF Data Output Propagation Delay 11 ns
t
XCTL
Clock to CTL
X
Output Propagation Delay 6.7 ns
Notes
17. Dashed lines denote signals with programmable polarity.
18. GPIF asynchronous RDY
x
signals have a minimum set-up time of 50 ns when using internal 48 MHz IFCLK.
19. IFCLK must not exceed 48 MHz.
Table 9-2. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK
[18]
Parameter Description Min. Max. Unit
t
IFCLK
IFCLK Period
[19]
20.83 200 ns
t
SRY
RDY
X
to Clock Set-up Time 2.9 ns
t
RYH
Clock to RDY
X
3.7 ns
t
SGD
GPIF Data to Clock Set-up Time 3.2 ns
t
DAH
GPIF Data Hold Time 4.5 ns
t
XGD
Clock to GPIF Data Output Propagation Delay 15 ns
t
XCTL
Clock to CTL
X
Output Propagation Delay 13.06 ns
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