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PRELIMINARY

CY7C1333H

Document #: 001-00209 Rev. **

Page 11 of 12

© Cypress Semiconductor Corporation, 2004. The information contained herein is subject  to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

NoBL and No Bus Latency are trademarks of Cypress Semiconductor. ZBT is a trademark of Integrated Device Technology. All
product and company names mentioned in this document are the trademarks of their respective holders.

 

Package Diagram 

100-lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

51-85050-*A

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Содержание CY7C1333H

Страница 1: ...ith data being transferred on every clock cycle This feature dramatically improves the throughput of data through the SRAM especially in systems that require frequent Write Read transitions All synchr...

Страница 2: ...B DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA NC NC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS V...

Страница 3: ...e allowed to behave as outputs When deasserted HIGH I O pins are three stated and act as input data pins OE is masked during the data portion of a Write sequence during the first clock when emerging f...

Страница 4: ...n incremented sufficiently A HIGH input on ADV LD will increment the internal burst counter regardless of the state of chip enable inputs or WE WE is latched at the beginning of a burst cycle Therefor...

Страница 5: ...t X X X L H X X L L L H Data Out Q NOP DUMMY READ Begin Burst External L H L L L H X H L L H Three State DUMMY READ Continue Burst Next X X X L H X X H L L H Three State WRITE Cycle Begin Burst Extern...

Страница 6: ...12 Truth Table for Read Write 2 3 Function WE BWA BWB BWC BWD Read H X X X X Write No Bytes Written L H H H H Write Byte A DQA L L H H H Write Byte B DQB L H L H H Write Byte C DQC L H H L H Write By...

Страница 7: ...Current GND VI VDD Output Disabled 5 5 A IDD VDD Operating Supply Current VDD Max IOUT 0 mA f fMAX 1 tCYC 7 5 ns cycle 133 MHz 225 mA 10 ns cycle 100 MHz 205 mA ISB1 Automatic CE Power down Current T...

Страница 8: ...2 0 ns tCENS CEN Set up before CLK Rise 1 5 2 0 ns tDS Data Input Set up before CLK Rise 1 5 2 0 ns tCES Chip Enable Set Up before CLK Rise 1 5 2 0 ns Notes 12 Timing reference level is 1 5V when VDD...

Страница 9: ...n CE is HIGH CE1 is HIGH or CE2 is LOW or CE3 is HIGH 20 Order of the Burst sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional Switching Characterist...

Страница 10: ...133AXC A101 Lead Free 100 lead Thin Quad Flat Pack 14 x 20 x 1 4 mm Commercial CY7C1333H 133AXI A101 Lead Free 100 lead Thin Quad Flat Pack 14 x 20 x 1 4 mm Industrial 100 CY7C1333H 100AXC A101 Lead F...

Страница 11: ...s written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to...

Страница 12: ...Page 12 of 12 Document History Page Document Title CY7C1333H 2 Mbit 64K x 32 Flow Through SRAM with NoBL Architecture Document Number 001 00209 REV ECN NO Issue Date Orig of Change Description of Chan...

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