Cypress Semiconductor CY7C1333H, Техническое описание

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PRELIMINARY
CY7C1333H
Document #: 001-00209 Rev. ** Page 8 of 12
Capacitance
[11]
Parameter Description Test Conditions 100 TQFP Package Unit
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz,
V
DD
= 3.3V
V
DDQ
=3.3V
5 pF
C
CLOCK
Clock Input Capacitance 5 pF
C
I/O
I/O Capacitance 5 pF
AC Test Loads and Waveforms
Switching Characteristics
Over the Operating Range
[12, 13]
Parameter Description
133 MHz 100 MHz
Unit Min. Max. Min. Max.
t
POWER
V
DD
(Typical) to the First Access
[14]
1 1 ms
Clock
t
CYC
Clock Cycle Time 7.5 10 ns
t
CH
Clock HIGH 2.5 4.0 ns
t
CL
Clock LOW 2.5 4.0 ns
Output Times
t
CDV
Data Output Valid after CLK Rise 6.5 8.0 ns
t
DOH
Data Output Hold after CLK Rise 2.0 2.0 ns
t
CLZ
Clock to Low-Z
[15, 16, 17]
0 0 ns
t
CHZ
Clock to High-Z
15, 16, 17]
3.5 3.5 ns
t
OEV
OE LOW to Output Valid 3.5 3.5 ns
t
OELZ
OE LOW to Output Low-Z
[15, 16, 17]
0 0 ns
t
OEHZ
OE HIGH to Output High-Z
[15, 16, 17]
3.5 3.5 ns
Set-up Times
t
AS
Address Set-up before CLK Rise 1.5 2.0 ns
t
ALS
ADV/LD Set-up before CLK Rise 1.5 2.0 ns
t
WES
WE, BW
[A:D]
Set-up before CLK Rise 1.5 2.0 ns
t
CENS
CEN Set-up before CLK Rise 1.5 2.0 ns
t
DS
Data Input Set-up before CLK Rise 1.5 2.0 ns
t
CES
Chip Enable Set-Up before CLK Rise 1.5 2.0 ns
Notes:
12. Timing reference level is 1.5V when V
DDQ
=3.3V
13. Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
14. This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
minimum initially before a Read or Write operation
can be initiated.
15. t
CHZ
, t
CLZ
,t
OELZ
, and t
OEHZ
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
16. At any given voltage and temperature, t
OEHZ
is less than t
OELZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve Three-state prior to Low-Z under the same system conditions
17. This parameter is sampled and not 100% tested.
OUTPUT
R = 317
Ω
R = 351
Ω
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Ω
Z
0
= 50
Ω
V
L
= 1.5V
3.3V
ALL INPUT PULSES
V
DDQ
GND
90%
10%
90%
10%
≤
1 ns
≤
1 ns
(c)
3.3V I/O Test Load
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