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CY7C1310AV18

CY7C1312AV18

CY7C1314AV18

 PRELIMINARY

Document #: 38-05497 Rev. *A

Page 6 of 21

Introduction

Functional Overview

The CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 are

synchronous pipelined Burst SRAMs equipped with both a

Read port and a Write port. The Read port is dedicated to

Read operations and the Write port is dedicated to Write

operations. Data flows into the SRAM through the Write port

and out through the Read Port. These devices multiplex the

address inputs in order to minimize the number of address pins

required. By having separate Read and Write ports, the QDR-II

completely eliminates the need to “turn-around” the data bus

and avoids any possible data contention, thereby simplifying

system design. Each access consists of two 8-bit data

transfers in the case of CY7C1310AV18, two 18-bit data

transfers in the case of CY7C1312AV18 and two 36-bit data

transfers in the case of CY7C1314AV18, in one clock cycles. 
Accesses for both ports are initiated on the rising edge of the

positive Input Clock (K). All synchronous input timings are

referenced from the rising edge of the input clocks (K and K)

and all output timings are referenced to the rising edge of

output clocks (C and C or K and K when in single clock mode).
All synchronous data inputs (D

[x:0]

) inputs pass through input

registers controlled by the input clocks (K and K). All

synchronous data outputs (Q

[x:0]

) outputs pass through output

registers controlled by the rising edge of the output clocks (C

and C or K and K when in single clock mode). 
All synchronous control (RPS, WPS, BWS

[x:0]

) inputs pass

through input registers controlled by the rising edge of the

input clocks (K and K). 
CY7C1312AV18 is described in the following sections. The

same basic descriptions apply to CY7C1310AV18 and

CY7C1314AV18. 

Read Operations

The CY7C1312AV18 is organized internally as two arrays of

512Kx18. Accesses are completed in a burst of two sequential

18-bit data words. Read operations are initiated by asserting

RPS

 

active at the rising edge of the Positive Input Clock (K).

The address is latched on the rising edge of the K Clock. The

address presented to Address inputs is stored in the Read

address register. Following the next K clock rise the corre-

sponding lowest order 18-bit word of data is driven onto the

Q

[17:0]

 using C as the output timing reference. On the subse-

quent rising edge of C, the next 18-bit data word is driven onto

the Q

[17:0]

. The requested data will be valid 0.45 ns from the

rising edge of the output clock (C and C or K and K when in

single clock mode). 
Synchronous internal circuitry will automatically tri-state the

outputs following the next rising edge of the Output Clocks

(C/C). This will allow for a seamless transition between

devices without the insertion of wait states in a depth

expanded memory. 

Write Operations

Write operations are initiated by asserting WPS active at the

rising edge of the Positive Input Clock (K). On the same K

clock rise, the data presented to D

[17:0]

 is latched and stored

into the lower 18-bit Write Data register provided BWS

[1:0]

 are

both asserted active. On the subsequent rising edge of the

Negative Input Clock (K), the address is latched and the infor-

mation presented to D

[17:0]

 is stored into the Write Data

Register provided BWS

[1:0]

 are both asserted active. The 36

bits of data are then written into the memory array at the

specified location. When deselected, the write port will ignore

all inputs after the pending Write operations have been

completed. 

Byte Write Operations

Byte Write operations are supported by the CY7C1312AV18.

A write operation is initiated as described in the Write

Operation section above. The bytes that are written are deter-

mined by BWS

0

 and BWS

1

 which are sampled with each 18-bit

data word. Asserting the appropriate Byte Write Select input

during the data portion of a write will allow the data being

presented to be latched and written into the device.

Deasserting the Byte Write Select input during the data portion

of a write will allow the data stored in the device for that byte

to remain unaltered. This feature can be used to simplify

Read/Modify/Write operations to a Byte Write operation.

Single Clock Mode

The CY7C1312AV18 can be used with a single clock that

controls both the input and output registers. In this mode, the

device will recognize only a single pair of input clocks (K and

K) that control both the input and output registers. This

operation is identical to the operation if the device had zero

skew between the K/K and C/C clocks. All timing parameters

remain the same in this mode. To use this mode of operation,

the user must tie C and C HIGH at power on. This function is

a strap option and not alterable during device operation.

Concurrent Transactions

The Read and Write ports on the CY7C1312AV18 operate

completely independently of one another. Since each port

latches the address inputs on different clock edges, the user

can Read or Write to any location, regardless of the trans-

action on the other port. Also, reads and writes can be started

in the same clock cycle. If the ports access the same location

at the same time, the SRAM will deliver the most recent infor-

mation associated with the specified address location. This

includes forwarding data from a Write cycle that was initiated

on the previous K clock rise.

V

REF

Input-

Reference

Reference Voltage Input

. Static input used to set the reference level for HSTL inputs 

and Outputs as well as AC measurement points.

V

DD

Power Supply

Power supply inputs to the core of the device

V

SS

Ground

Ground for the device

V

DDQ

Power Supply

Power supply inputs for the outputs of the device

Pin Definitions 

 (continued)

Pin Name

I/O

Pin Description

[+] Feedback 

Содержание CY7C1310AV18

Страница 1: ...ead operations and the Write Port has dedicated Data Inputs to support Write opera tions QDR II architecture has separate data inputs and data outputs to completely eliminate the need to turn around t...

Страница 2: ...ata Reg RPS WPS Q 17 0 Control Logic Address Register Reg Reg Reg 18 19 18 36 18 BWS 1 0 VREF Write Add Decode 18 A 18 0 19 C C 18 512K x 18 Array 512K x 18 Array Write Reg Write Reg CQ CQ 18 DOFF Log...

Страница 3: ...VREF NC NC VDDQ NC VDDQ NC NC VDDQ VDDQ VDDQ D1 VDDQ NC Q1 NC VDDQ VDDQ NC VSS NC D0 NC TDI TMS VSS A NC A NC D2 NC ZQ NC Q0 NC NC NC NC A CY7C1312AV18 1M 18 11 15 BGA 2 3 4 5 6 7 1 A B C D E F G H J...

Страница 4: ...tten into the device A Input Synchronous Address Inputs Sampled on the rising edge of the K read address and K write address clocks during active read and write operations These address inputs are mul...

Страница 5: ...to drive out data through Q x 0 when in single clock mode CQ Echo Clock CQ is referenced with respect to C This is a free running clock and is synchronized to the output clock C of the QDR II In the s...

Страница 6: ...on of wait states in a depth expanded memory Write Operations Write operations are initiated by asserting WPS active at the rising edge of the Positive Input Clock K On the same K clock rise the data...

Страница 7: ...et by slowing the cycle time of input clocks K and K to greater than 30 ns Application Example 1 Truth Table 2 3 4 5 6 7 Operation K RPS WPS DQ DQ Write Cycle Load address on the rising edge of K cloc...

Страница 8: ...es during this portion of a write operation H H L H No data is written into the devices during this portion of a write operation Write Cycle Descriptions CY7C1314AV18 2 8 BWS0 BWS1 BWS2 BWS3 K K Comme...

Страница 9: ...t LOW Voltage 12 13 0 3 VREF 0 1 V VIN Clock Input Voltage 0 3 VDDQ 0 3 V IX Input Load Current GND VI VDDQ 5 5 A IOZ Output Leakage Current GND VI VDDQ Output Disabled 5 5 A VREF InputReferenceVoltag...

Страница 10: ...tCQOH tCHCQX Echo Clock Hold after C C Clock Rise 0 50 0 50 ns tCQD tCQHQV Echo Clock High to Data Valid 0 40 0 40 ns tCQDOH tCQHQX Echo Clock High to Data Invalid 0 40 0 40 ns tCHZ tCHZ Clock C and C...

Страница 11: ...CCLK Clock Input Capacitance 6 pF CO Output Capacitance 7 pF AC Test Loads and Waveforms Note 20 Tested initially and after any design or process change that may affect these parameters 1 25V 0 25V R...

Страница 12: ...if address A2 A1 then data Q20 D10 and Q21 D11 Write data is forwarded immediately as read results This note applies to the whole diagram Read Write Deselect Sequence K 1 2 3 4 5 8 10 6 7 K RPS WPS A...

Страница 13: ...is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruct...

Страница 14: ...ter between the TDI and TDO pins PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells pri or to the selection of another boundary sca...

Страница 15: ...ents the value at TMS at the rising edge of TCK TAP Controller State Diagram 24 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR SELECT IR SCAN...

Страница 16: ...tage IOL 2 0 mA 0 4 V VOL2 Output LOW Voltage IOL 100 A 0 2 V VIH Input HIGH Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and OutputLoad Current GND VI VDD 5 5 A Note 25 Thes...

Страница 17: ...imes tTMSH TMS Hold after TCK Clock Rise 10 ns tTDIH TDI Hold after Clock Rise 10 ns tCH Capture Hold after Clock Rise 10 ns Output Times tTDOV TCK Clock LOW to TDO Valid 20 ns tTDOX TCK Clock LOW to...

Страница 18: ...dor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z 010 Captures the Input Output contents Places the boundary scan register between TDI and...

Страница 19: ...1 6C 52 8A 53 7A 54 7B 55 6B 56 6A 57 5B 58 5A 59 4A 60 5C 61 4B 62 3A 63 1H 64 1A 65 2B 66 3B 67 1C 68 1B 69 3D 70 3C 71 1D 72 2C 73 3E Boundary Scan Order continued Bit Bump ID 74 2D 75 2E 76 1E 77...

Страница 20: ...names mentioned in this document are the trademarks of their respective holders Ordering Information Speed MHz Ordering Code Package Name Package Type Operating Range 167 CY7C1310AV18 167BZC BB165D 13...

Страница 21: ...nt History Page Document Title CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 18 Mb QDR II SRAM 2 Word Burst Architecture Document Number 38 05497 REV ECN No Issue Date Orig of Change Description of Change 20...

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