CYPRES WICED CYW920706WCDEVAL, Руководство пользователя по оборудованию

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Interface Signal Function Selection Restrictions and Considerations
CYW920706WCDEVAL Hardware User Guide Doc. No.: 002-16535 Rev. ** 30
9.2.1 SPI1
The application has full control of the SPI1 interface. The SPI1 interface supports:

SPI clock modes 0 through 4.

A maximum transaction size of 254 bytes.

A maximum clock speed of 12 MHz for all I/O supply levels.
Note: Running the SPI clock at speeds above 12 MHz can lead to undesired behavior.

Configuration as either a master or a slave.
SPI1 bus-configuration options are detailed in the SPI1 Master and SPI1 Slave sections.
9.2.1.1 SPI1 Master
With SPI1 configured as a master, multiple slaves can be connected to the same bus, where the clock (SPI1_CLK), data input
(SPI1_MISO), and data output (SPI1_MOSI) lines comprise the bus.
An LHL GPIO signal will need to be assigned to source each required slave chip-select output.
The application controls Chip Select (CS) line assertion and de-assertion and can use the CS line to optimize transactions
greater than 254 bytes.
Note: The software application controls the chip selects using a GPIO driver provided by the WICED Studio API. See Section
10 “ Interface Programming Information and Examples ” for more information.
Table 9-2 shows CYW20706 SPI1 master bus-configuration options.
Option
SPI1_CLK SPI1_MOSI SPI1_MISO
Pin LHL GPIOPxx Pin LHL GPIO Pxx Pin LHL GPIO Pxx
1 G8 P24 C5 P27 F7 P25
2 G8 P24 F8 P38 F7 P25
3 F8 P36 C5 P27 F7 P25
Table 9-2. CYW20706 SPI1 Master Bus-Configuration Options
Note: The RX signal of a peripheral UART (PUART) has certain restrictions if included in a system design that also uses the
SPI1 interface. See Section 9.4 “ Peripheral UART ” to understand how this restriction affects the bus configuration options of
both interfaces.
For a SPI1 master programming example, see Section 10.2 “ SPI1 Master Programming Example ”.