3. Theory of Operation
The CSA
Mega-Midget Racer
accelerator replaces the MC68000 CPU in the
Amiga and utilizes an MC68030 microprocessor as its main CPU. The
MC68030 is operated asynchronously to the Amiga system, which allows
the
Mega-Midget Racer
to operate at many frequencies. This asynchronous
operation requires that the accelerator must provide a synchronous bus
i n t e r f a c e t o t h e A m i g a s y s t e m . T h i s i s a c c o m p l i s h e d w i t h t h e
M e g a -
Midget Racer’s
MC68000 bus interface emulator.
The MC68000 bus interface emulator is responsible for reproducing all of
the MC68000 bus signals when an access to the Amiga system is required.
When the MC68030 is accessing one of the resources within the
Mega-
Midget Racer’s
environment (FPU, SRAM, 32-bit expansion bus, etc...), the
emulator must hide the access from the Amiga system.
The Amiga system operates at a basic frequency of about 7 MHz, while the
Mega-Midget Racer
operates at frequencies between 20 and 33 MHz. In
general, an access to the Amiga system is much slower than an access to
one of the resources in the MC68030’s environment. Therefore, the more
resources that are installed in the MC68030 environment, the better the
performance of the entire system.
Besides the MC68000 bus interface emulator, the
Mega-Midget Racer
has
several areas of special logic: the CPU/FPU interface, the expansion bus
interface, the SRAM interface and wait-state generator, the MC68000
compatibility-mode circuitry, and the cache control logic. Each of these
areas have special considerations and therefore require special logic.
Every
Mega-Midget Racer
fully implements all of this special logic, no
matter what resources are installed. This allows the user to add, remove,
or upgrade any of the user installable resources without having to have
the board modified for each configuration.
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