The SROM option copies the Amiga ROM kernel into the 32-bit SRAM on the
Mega-Midget
Racer
and enables a hardware feature that allows the ROM kernel to be executed out of
the fast, 32-bit RAM without the use of the MC68030’s Memory Management Unit
(MMU). Depending on the size of the ROM, either 256k or 512k bytes of the 512k byte
SRAM area will be used. If both the SROM and SRAM options are specified, the SROM will
be installed first. Any remaining SRAM will be added to the system as fast memory. If
the SRAM option is specified without the SROM option, then all 512k bytes of SRAM will
be added to the system as fast memory.
The DRAM option checks for the presence of the CSA
Mega-Memory
DRAM daughter-
board, configures the DRAM controller, tests the DRAM memory, and adds the DRAM to
the system as fast memory. The clock frequency of the
Mega-Midget Racer
is needed to
properly configure the DRAM controller. The default is 25.00 MHz and can be specified
as any value between 20.00 and 33.33 MHz. Information about the type, size, and speed
of the DRAM chips and the number of banks is automatically retrieved from the jumper
settings on the daughter-board.
T h e f o l l o w i n g p r o g r a m s a r e u s e f u l i n m a n i p u l a t i n g t h e
M e g a - M i d g e t
Racer’s
resources.
Amiga_Status: (Icon)
Running the Amiga_Status program displays information about the current system
configuration. The program displays the processor and co-processor types, indicates
which caches are enabled or disabled, and indicates whether or not the MMU is in use.
This program may be run at anytime from the CLI or from the Workbench (by double-
clicking on the Icon).
Clear_CACR: (Icon)
Running the Clear_CACR program clears the MC68030’s Cache Control Register, which
has the effect of disabling both the instruction and data caches. This program may be run
at anytime from the CLI or from the Workbench (by double-clicking on the Icon).
Switch_ICache: (Icon)
Running the Switch_ICache program toggles the MC68030’s instruction cache enable bit
in the Cache Control Register. This has the effect of enabling or disabling the instruction
cache. This program may be run at anytime from the CLI or from the Workbench (by
double-clicking on the Icon).
Switch_DCache: (Icon)
Running the Switch_DCache program toggles the MC68030’s data cache enable bit in the
Cache Control Register. This has the effect of enabling or disabling the data cache. This
program may be run at anytime from the CLI or from the Workbench (by double-
clicking on the Icon). The CSA-MMR program (described above) must be run before the
Swttch_DCache program will function properly.
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