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CS5521 CS5523

DS317PP2

Channel-Setup Registers

* R indicates the bit value after the part is reset

CSR (Channel-Setup Register)

CSR

LC (Log. Channel) 1

Bits <47:36>

LC 2

Bits <35:24>

LC 1

Bits <95:84>

LC 2

Bits <83:72>

LC 3

Bits <23:12>

LC 4

Bits <11:0>

LC 7

Bits <23:12>

LC 8

Bits <11:0>

CS5521

CS5523

D23(MSB)

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

CS1

CS0

WR2

WR1

WR0

U/B

D11

D10

CS1

CS0

WR2

WR1

WR0

U/B

BIT

NAME

VALUE

FUNCTION

D23/D11-
D22/D10

Latch Outputs, A1-A0

*R Latch Output Pins A1-A0 mimic D23/D11-D22/D10 register bits.

D21/D9

Not Used, NU

R Must always be logic zero.

D20/D8-
D19/D7

Channel Select, CS1-
CS0

00
01
10

R Select physical channel 1.

Select physical channel 2.
Select physical channel 3.
Select physical channel 4.

D18/D6-
D16/D4

Word Rate, WR2-WR0

000
001
010
011
100
101
110

111

R 15.0 Hz (2180 XIN cycles).

30.0 Hz (1092 XIN cycles).
61.6 Hz (532 XIN cycles).
84.5 Hz (388 XIN cycles).
101.1 Hz (324 XIN cycles).
1.88 Hz (17444 XIN cycles).
3.76 Hz (8724 XIN cycles).
7.51 Hz (4364 XIN cycles).

D15/D3-
D13/D1

Gain Bits, G2-G0

000
001
010
011
100
101
110

111

R 100 mV (assumes VREF Differential = 2.5 V)

55 mV
25 mV
1.0 V
5.0 V
2.5 V
Not used.
Not used.

D12/D0

Unipolar/Bipolar, U/B

0
1

R Bipolar measurement mode.

Unipolar measurement mode.

Table 3. Channel-Setup Registers

Содержание CS5521-AP

Страница 1: ...which include an instrumentation amplifier a PGA programmable gain amplifier a multi channel multiplexer digital filters and self and system calibration circuitry The chips are designed to provide th...

Страница 2: ...duct information describes products which are in production but for which full characterization data is not yet available Advance product information describes products which are in development and su...

Страница 3: ...Command and Data Word Timing 15 Multiplexer Configuration 22 Input models for AIN and AIN pins for each range 24 Input model for VREF and VREF pins 24 Self Calibration of Offset Low Ranges 26 Self Ca...

Страница 4: ...t ranges 100 mV and output rates 61 6 Hz 16 384 kHz chopping frequency is used Parameter Min Typ Max Unit Accuracy Resolution 16 Bits Linearity Error 0 0015 0 003 FS Bipolar Offset Note 3 1 2 LSB16 Un...

Страница 5: ...mmon Mode Rejection dc 50 60 Hz 120 120 dB dB Input Capacitance 10 pF CVF Current on AIN or AIN Note 5 Range 25 mV 55 mV or 100 mV Range 1 V 2 5 V or 5 V 100 10 300 pA nA System Calibration Specificat...

Страница 6: ...0 VD 1 0 VD 1 0 V V V Low Level Output Voltage All Pins Except CPD and SDO Iout 1 6 mA CPD Iout 2 mA SDO Iout 5 0 mA VOL 0 4 0 4 0 4 V V V Input Leakage Current Iin 1 10 A 3 State Leakage Current IOZ...

Страница 7: ...ed at these extremes Parameter Symbol Ratio Unit Modulator Sampling Frequency fs XIN 4 Hz Filter Settling Time to 1 2 LSB Full Scale Step ts 1 fout s Parameter Symbol Min Typ Max Unit DC Power Supplie...

Страница 8: ...scillator XIN 30 32 768 100 kHz Master Clock Duty Cycle 40 60 Rise Times Note 20 Any Digital Input Except SCLK SCLK Any Digital Output trise 50 1 0 100 s s ns Fall Times Note 20 Any Digital Input Exce...

Страница 9: ...7PP2 9 CS SCLK t0 t2 t1 t3 t6 Continuous Running SCLK Timing Not to Scale CS SCLK MSB MSB 1 LSB SDI t3 t4 t5 t1 t2 t6 SDI Write Timing Not to Scale CS SCLK MSB MSB 1 LSB SDO t7 t8 t1 t2 t9 SDO Read Ti...

Страница 10: ...23 A D converters are designed to op erate from a single 5 V analog supply with several different input ranges See the Analog Character istics section on page 3 for details Figure 1 illustrates the CS...

Страница 11: ...ts Figure 5 illustrates the CS5521 23 connected to measure the output of a ratiometric differential bridge transducer while operating from a single 5 V supply 5V NBV 30 1K 34 8K 2N5087 or similar 5V 2...

Страница 12: ...er for each input channel The serial port also includes a programmable channel sequencer which can se quence up to 8 channels to be converted The se quencer consists of channel setup registers CSRs wh...

Страница 13: ...s SCLK is designed with a Schmitt trigger input to allow an optoisola tor with slower rise and fall times to directly drive the pin Additionally SDO is capable of sinking or sourcing up to 5 mA to dir...

Страница 14: ...ster Conversion Data FIFO read only Channel Set up Registers register is 48 bits long for CS5521 register is 96 bits long for CS5523 Reserved Reserved Table 1 Command Set with MSB 0 D7 MSB D6 D5 D4 D3...

Страница 15: ...LKs CS SCLK SDI Data Time 24 SCLKs Read Cycle SDO MSB LSB Command Time 8 SCLKs 8 SCLKs Clear SDO Flag SDO SCLK SDI Data Time 24 SCLKs MSB LSB td XIN OWR clock cycles for each conversion except the fir...

Страница 16: ...D23 D11 D22 D10 register bits D21 D9 Not Used NU 0 R Must always be logic zero D20 D8 D19 D7 Channel Select CS1 CS0 00 01 10 11 R Select physical channel 1 Select physical channel 2 Select physical c...

Страница 17: ...Refer to Calibration Protocol for details D15 Not Used NU 0 R Must always be logic 0 D14 D12 Depth Pointer DP2 DP0 000 111 R When writing or reading the CSRs these bits DP2 DP0 determine the number o...

Страница 18: ...nel While in this mode the user may choose to acquire only the conversions required for his application as SDO rises and falls to indicate the availability of a new conversion To exit this conversion...

Страница 19: ...is case SDO rises and falls once a new set of conversions is complete to indicate that a new set of data is ready to acquire or 3 read the conversion data FIFO and remain in this mode this is accom pl...

Страница 20: ...nversions on six logical channels The order in which the channels are converted is 4 1 4 2 4 3 SDO falls after physical channel 3 is converted To acquire the 6 conversions 8 SCLKs with SDI 0 are re qu...

Страница 21: ...sical chan nel 4 in this example SDO falls after physical channel 4 is converted To read the conversion 32 SCLKs are then required Once acquired the serial port returns to the command mode Example 5 T...

Страница 22: ...1 23 can accommodate full scale ranges other than 25 mV 55 mV 100 mV 1 V 2 5 V and 5 V by performing a system calibration within the limits specified See the Calibration section for more details Anoth...

Страница 23: ...the AIN and AIN pins remains constant for the three low level mea surement ranges 25 mV 55 mV and 100 mV The input current is lowest with the CFS bits cleared to logic 0s Note Residual noise appears i...

Страница 24: ...s of the device For a single ended refer ence voltage such as the LT1019 2 5 the reference voltage is input into the VREF pin of the convert er and the VREF pin is grounded The differential voltage be...

Страница 25: ...ange the converter s gain er ror can not be completely calibrated out This is due to the lack of an accurate full scale voltage internal to the chips The 2 5 V range is an exception be cause the exter...

Страница 26: ...exceed 3 9999998 see the discussion of operating limits on input span under the Analog Input and Limita tions in Calibration Range sections The above conditions require the full scale input voltage to...

Страница 27: ...it 2 s complement Cg Gain calibration register value 24 bit integer Calibration Tips Calibration steps are performed at the output word rate selected by the WR2 WR0 bits of the configu ration register...

Страница 28: ...te of the converter as shown in Table 4 The word rates indicated in the table assume a master clock of 32 768 kHz Upon reset the converter is set to operate with an output word rate of 15 0 Hz Clock G...

Страница 29: ...The power save modes are entered whenever the PS R bit of the configuration register is set to logic 1 The particular power save mode entered depends on state of bit D11 PSS the Power Save Select bit...

Страница 30: ...medi ately adjacent to the digital portion of the chip If separate digital VD and analog VA supplies are used it is recommended that a diode be placed between them the cathode of the diode should poin...

Страница 31: ...LOGIC OUTPUT NEGATIVE BIAS VOLTAGE DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT POSITIVE ANALOG POWER ANALOG GROUND CRYSTAL IN CHIP SELECT VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT DIFFER...

Страница 32: ...input pins into the CS5521 and CS5523 devices VREF VREF Voltage Reference Input Fully differential inputs which establish the voltage reference for the on chip modulator NBV Negative Bias Voltage Inp...

Страница 33: ...ansition from the ideal VREF VREF 3 2 LSB Units are in LSBs Unipolar Offset The deviation of the first code transition from the ideal 1 2 LSB above the voltage on the AIN pin When in unipolar mode U B...

Страница 34: ...el 3 Dimension E does not include mold flash INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0 155 0 180 3 94 4 57 A1 0 020 0 040 0 51 1 02 b 0 015 0 022 0 38 0 56 b1 0 050 0 065 1 27 1 65 c 0 008 0 015 0 20...

Страница 35: ...sion E does not include mold flash INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0 155 0 180 3 94 4 57 A1 0 020 0 040 0 51 1 02 b 0 014 0 022 0 36 0 56 b1 0 040 0 065 1 02 1 65 c 0 008 0 015 0 20 0 38 D 1...

Страница 36: ...material condition Dambar intrusion shall not reduce dimension b by more than 0 07 mm at least material condition 3 These dimensions apply to the flat section of the lead between 0 10 and 0 25 mm fro...

Страница 37: ...material condition Dambar intrusion shall not reduce dimension b by more than 0 07 mm at least material condition 3 These dimensions apply to the flat section of the lead between 0 10 and 0 25 mm fro...

Страница 38: ...cation may be copied reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photographic or otherwise without the prior written consent of Cirrus Logi...

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