Crystal CS4231A, Руководство пользователя

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TIMING PARAMETERS
(T
A
= 25 °C; VA1, VA2, VD1-VD4 = +5V, outputs loaded with 30 pF;
Input Levels: Logic 0 = 0V, Logic 1 = VD1-VD4)
Parameter Symbol Min Max Units
WR or RD strobe width t
STW
90 ns
Data valid to WR rising edge (write cycle) t
WDSU
22 ns
RD falling edge to data valid (read cycle) t
RDDV
60 ns
CS setup to WR of RD falling edge t
CSSU
10 ns
CS hold from WR or RD rising edge t
CSHD
0 ns
ADDR <> setup to RD or WR falling edge t
ADSU
22 ns
ADDR <> hold from WR or RD rising edge t
ADHD
10 ns
DAK inactive to WR or RD falling edge (DMA cycle
completion immediately followed by a non-DMA cycle) t
SUDK1
60 ns
DAK active from WR or RD rising edge (non-DMA cycle
completion immediately followed by DMA cycle) t
SUDK2
0 ns
DAK setup to RD falling edge (DMA cycles)
DAK setup to WR falling edge t
DKSUa
t
DKSUb
25
25 ns
ns
Data hold from WR rising edge t
DHD2
15 ns
DRQ hold from WR or RD falling edge
(assumes no more DMA cycles needed) t
DRHD
0 25 ns
Time between rising edge of WR or RD to next falling edge
of WR or RD t
BWND
80 ns
Data hold from RD rising edge t
DHD1
0 20 ns
DAK hold from WR rising edge
DAK hold from RD rising edge t
DKHDa
t
DKHDb
25
25 ns
ns
DBEN or DBDIR active from WR or RD falling edge t
DBDL
40 ns
PDWN pulse width low t
PDWN
200 ns
Crystals, XTAL1I, XTAL2I frequency (Notes 1,7,8) 25.6 MHz
XTAL1I, XTAL2I high time (Notes 1,8) 18 ns
XTAL1I, XTAL2I low time (Notes 1,8) 18 ns
Sample frequency (Note 1) Fs 5.5 50 kHz
Serial Port Timing
SCLK frequency (Note 9) t
SCLKW
Fsx64 Hz
SCLK rising to SDOUT valid t
PD1
30 ns
SCLK rising to FSYNC transition t
PD2
-20 20 ns
SDIN valid to SCLK falling t
S1
30 ns
SDIN hold after SCLK falling t
H1
30 ns
Notes: 7. When only one crystal is used, it must be XTAL1. When using two crystals, the high frequency
crystal should be on XTAL1 which is designed for higher loop gains.
8. Sample frequency specifications must not be exceeded.
9. When SF1, 0 = 10, 32-bit mode, SCLK is active for the first 32 bit periods of the frame, and remains
low during the last 32 bit periods of the frame.
CS4231A
DS139PP2 7