Crystal CS4231A, Руководство пользователя

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WR or RD strobe of a full sample of a DMA
cycle occurs, the DMA request signal is negated
immediately. DMA transfers may be terminated
by resetting the PEN and/or CEN bits in the In-
terface Configuration register (I9), depending on
the DMA that is in progress (playback, capture,
or both). Termination of DMA transfers may
only happen between sample transfers on the
bus. If PDRQ and/or CDRQ goes active while
resetting PEN and/or CEN, the request must be
acknowledged (PDAK and/or CDAK) and a fi-
nal sample transfer completed. The CS4231A
supports up to two DMA channels.
Dual DMA Channel Mode
In dual DMA channel mode, playback and cap-
ture DMA requests and acknowledges occur on
independent DMA channels. In this mode, cap-
ture and playback are enabled and set for DMA
transfers. In addition, the dual DMA mode must
be set (SDC = 0). The Playback- and Capture-
Enables (PEN, CEN, I9) can be changed without
a Mode Change Enable (MCE, R0). This allows
for proper full duplex control where applications
are independently using playback and capture.
Single DMA Channel (SDC) Mode
When two DMA channels are not available, the
SDC mode forces all DMA transfers (capture or
playback) to occur on a single DMA channel
(playback channel). The trade-off is that the
CS4231A will no longer be able to perform si-
multaneous DMA capture and playback.
To enable the SDC mode, set the SDC bit in the
Interface Configuration register (I9). With the
SDC bit asserted, the internal workings of the
CS4231A remain exactly the same as dual mode,
except for the manner in which DMA request
and acknowledges are handled.
The playback of audio data will occur on the
playback channel exactly as dual channel opera-
tion. However, the capture audio channel is now
diverted to the playback channel. This means
that the capture DMA request occurs on the
PDRQ pin and the PDAK pin is used to acknow-
ledge the capture request. (In MODE 2, the
capture data format is always set in register I28.)
Note, simultaneous capture and playback cannot
occur in SDC mode. If both playback and cap-
ture are enabled, the default will be playback.
In SDC mode, the CDRQ pin is logic low (inac-
t ive ). T he CDAK p in i s i g no red by t he
CS4231A. SDC does not have any affect when
using PIO accesses.
Serial Audio Data Port
The bits controlling the serial port can only be
changed when the Mode Change Enable bit,
MCE, in R0 is high. The audio serial port is
software selectable via the SPE bit in I16. Once
enabled, the data from the ADCs is sent to the
SDOUT pin and the audio data input on the
SDIN pin is routed to the DACs. The parallel
bus on the CS4231A is still used for control in-
formation such as volume and audio data
formats. While the serial port is enabled, audio
data can still be read from the codec ADCs (cap-
ture) on the parallel port, but the DACs
(playback) only accept data from the serial port
i n p in. Whe n t he se rial po rt i s disabled
(SPE = 0); FSYNC, SCLK, and SDOUT are
held low.
FSYNC and SCLK are always output from the
CS4231A. The serial port can be configured in
one of three serial port formats, shown in Fig-
ures 6-8. SF1 and SF0 in I16 select the particular
format. Both left and right audio words are al-
ways 16 bits wide with the actual audio data left
justified in the word (i.e. ADPCM occupies the
first four bits). Unused bits are output as zeros
after the LSB. The justification is illustrated in
Figure 9. When the mono audio format is se-
lected, the right channel output is set to zero and
the left channel input is sent to both DAC chan-
nels. When changing sample frequencies the
CS4231A
16 DS139PP2