Cronologic Ndigo5G-10, Руководство пользователя

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3 for the version produced starting in 2011 labeled “Rev. 3”
int board configuration
Describes the schematic configuration of the board.
For board revision 0 this always reads 0.
For board revision 2 the following assignments are valid:
If Bit 3 = 0 this following is valid:
Bit 0 determines the ADC resolution. (0 = 8
− bit or 1 = 10 − bit ).
Bit 1 determines whether the TDC-oscillator is present (0 = oscillator present, 1 = simple trigger).
Bit 2 determines the input connectors (0 = single ended, 1 = differential).
Bit 3 = 1 signifies a special version of the board
0xA is Ndigo1250M-12 single ended with digital trigger
0x8 is Ndigo5G-8 single ended with digital trigger
For Board revision 3 the following assignments are valid:
Bit 2 determines the input connectors (0 = single ended, 1 = differential).
The other bits have one of the following patterns [Bits 3...0]
0010 Ndigo5G-10 2.5u 10
0011 Ndigo5G-8-AQ 2.5u 8
0110 Ndigo5G-10-Diff 560pF 10 DIFF
1000 Ndigo5G-8 560pF 8+
1010 Ndigo1250M-12 2.2uF 12 Sciex DC
1011 Ndigo5G-10 560pF 10
1110 Ndigo5G-Sciex 2.2uF 10 Sciex Infiniband, DIFF
1111 Ndigo5G-Roent = fADC4/10 560pF 10
int adc resolution
Number of bits of the ADC, set to 0 if unknown.
double nominal sample rate
Sample rate in once channel mode. Usually 5 . 0 e 9 = 5 Gsps .
double analog bandwidth
3e9 for 3Ghz
int chip id
16 bit factory ID of the ADC chip
int board serial
Serial number with the year minus 2000 in the highest 8 bits of the integer and a running number
in the lower 24 bits. This number is identical with the one on the label on the board.
int flash serial low
int flash serial high
64 bit manufacturer serial number of the flash chip.
int flash valid
If not 0 the driver found valid calibration data in the flash on the board and is using it.
ndigo bool t dc coupled
cronologic GmbH & Co. KG 28 Ndigo5G User Guide