Cronologic Ndigo5G-10, Руководство пользователя

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pre 1 cycles of 3.2ns. For level triggering, packet length is data dependent
(Figure
2.12 on page 12 ).
Please note that triggering is not accurate to sample. For each 3.2ns clock cycle, it is deter-
mined whether on any sample during that clock cycle a trigger condition is met. The clock cycle
is then selected as the trigger point. As a result, the trigger sample can be anywhere within a
range of up to 16 samples in single channel mode (Figure
2.15 on page 13 ) at 16 samples per
3.2ns.
If retriggering is active, the current trigger window is extended if a trigger event is detected
inside the window.
A trigger block can use several input sources:
ˆ
the 8 trigger decision units of all four ADC channels (Figure 2.16 on page 13 )
ˆ
the GATE input (Figure 2.17 on page 13 )
ˆ
the Trigger input (Figure 2.17 on page 13 )
ˆ
a function trigger providing random or periodic triggering (Section 2.4.5 on page 18 )
ˆ
triggers originating from other cards connected with the sync cable or from the Ndigo
Extension card (BUS0, BUS1, BUS2, BUS3)
ˆ
A second set of trigger units for the digital inputs Trigger, GATE, BUS0, BUS1, BUS2,
and BUS3 that is set in hardware to positive edge triggering. This set of triggers is not
available as inputs for the gate blocks.
Trigger inputs from the above sources can be concatenated using logical “OR” (Figure 2.19
on page 14 ) by setting the appropriate bits in the trigger blocks source mask.
Triggers can be fed into the gate blocks described on page 15 (Figure 2.20 ). Gate blocks can
be used to block writing data to the FIFO. That way, only zero suppressed data occurring when
the selected gate is active is transmitted. This procedure reduces PCIe bus load even further
(Figure
2.20 ).
precursor = 6 length = 12
total length = 19
th
re
sh
o
ld
Figure 2.11: Parameters for edge triggering
cronologic GmbH & Co. KG 11 Ndigo5G User Guide