Cronologic Ndigo5G-10 Скачать руководство пользователя страница 26 | Manualshive

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Figure 2.25: Histogram for the case the delay value for the board is not set correctly. Please

note: the lower panel might differ from board to board, with the “step” being at a
different position.

Figure 2.26: Histogram for the case the delay value for the board is set correctly. Please note: the

lower panel might differ from board to board, with the “step” being at a different
position.

cronologic GmbH & Co. KG

21

Ndigo5G User Guide

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Содержание Ndigo5G-10

Страница 1: ...Revision 1 0 8 as of 2018 11 19 Firmware 2 build 4865 Driver v1 3 0 cronologic GmbH Co KG Ndigo5G 8 Ndigo5G 10 User Guide cronologic...

Страница 2: ......

Страница 3: ......

Страница 4: ...d an HPTDC8 PCI 22 2 6 Performing a firmware update 22 2 7 Calibrating the TDC 23 3 Driver Programming API 25 3 1 Constants 25 3 2 Initialization 25 3 2 1 Structure ndigo init parameters 25 3 3 Status...

Страница 5: ...sps 45 6 1 3 4 Channel Mode 1 25 Gsps 46 6 2 Electrical Characteristics 46 6 2 1 Oscillator 46 6 2 2 Environmental Conditions for Operation 46 6 2 3 Environmental Conditions for Storage 46 6 2 4 Power...

Страница 6: ...a from a single trigger event together with a timestamp 1 1 Features 10 bit dynamic range up to 5 Gsps sample rate in 1 channel mode up to 4 channels digital input with TDC that can also be used for g...

Страница 7: ......

Страница 8: ...oduct line can be synced to other Ndigo boards allowing for instance for a combination of high speed ADCs Ndigo5G and slower high resolution ADCs Ndigo250M 14 or the upcoming Ndigo TDC The signals use...

Страница 9: ...uts A to D and the two digital inputs G GATE and T Trigger Furthermore two board interconnection connectors can be found at the top edge of the Ndigo5G as displayed in Figure 2 3 on page 5 Connector C...

Страница 10: ...moves the common mode voltage from the input signal Users can move the common mode voltage to a value of their choice using the analog offset parameter of each channel before sampling This feature is...

Страница 11: ...configurations structure to support positive and negative input pulses The configuration is set via the structures trigger 8 and trigger 9 in the configuration struc ture The input circuit is shown i...

Страница 12: ...0 AF9 Output 39 MHz clock for HPTDC LEMO00 CH4 6 AD11 Output 39 MHz clock for HPTDC LEMO00 CH5 5 AE7 Output 39 MHz clock for HPTDC LEMO00 CH6 9 AF7 Output 39 MHz clock for HPTDC LEMO00 CH7 13 D9 not c...

Страница 13: ...e 9 and Figure 2 14 on page 12 4 Channel Mode ABCD In this mode all four channels are digitized independently at 1 25Gsps each The packet size is always a multiple of 4 samples per 3 2ns See Figure 2...

Страница 14: ...C C 1 25 Gsps ADC D 1 25 Gsps AAI AAIN DAI DAIN In phase 1 25 GHz Figure 2 8 ADCs in 2 channel mode AD interleaved for 2 5Gsps CLK 72 5 GHz Clock circuit Inverted 1 25 GHz ADC A 1 25 Gsps ADC B 1 25 G...

Страница 15: ...record analog waveforms using zero suppression Whenever a rel evant waveform is detected data is written to an internal FIFO memory Each ADC channel has one trigger block determining whether data is...

Страница 16: ...3 a function trigger providing random or periodic triggering Section 2 4 5 on page 18 triggers originating from other cards connected with the sync cable or from the Ndigo Extension card BUS0 BUS1 BUS...

Страница 17: ...precursor 1 length 2 total length 4 threshold 3200 ps Figure 2 13 Triggering in 4 channel mode at 4 samples per clock cycle precursor 1 length 2 total length 4 threshold 3200 ps Figure 2 14 Triggering...

Страница 18: ...edge trigger 1 rising threshold Z 1 edge trigger 2 Figure 2 16 From the ADC inputs a trigger unit creates an input flag for the trigger matrix Each digitizer channel A B C D has two trigger units ris...

Страница 19: ...tal trigger gate gate_pe tdc_pe tdc A0 A1 B0 B1 C0 C1 D0 D1 digital trigger bus1 bus1_pe extension block sync1 ext1 digital trigger bus0 bus0_pe extension block sync0 ext0 digital trigger bus3 bus3_pe...

Страница 20: ...blocks can use the gate signal to suppress data acquisition Only data that fulfills zero suppression specifications occurring in an active gate window is written to the PC As input any trigger from th...

Страница 21: ...noise shall be suppressed Gating Example 2 Delayed Trigger To sample a short window at a specified time after a trigger event on a channel the gating block can be used to create a delayed trigger To d...

Страница 22: ...0 enabled 1 2 c o n f i g t r i g g e r b l o c k 0 p r e c u r s o r 2 3 c o n f i g t r i g g e r b l o c k 0 length 0 4 c o n f i g t r i g g e r b l o c k 0 sources NDIGO TRIGGER SOURCE ONE 5 c o...

Страница 23: ...the current trigger configuration does not trigger e g to get base line information in mass spectrometry applications It can also be used to determine a suitable threshold level for the trigger by fir...

Страница 24: ...hronization a delay parameter needs to be set for each board This parameter might change in case boards are swapped added or removed and in some cases might change after a firmware update The calibrat...

Страница 25: ...delay value of the current location is displayed 3 After stopping the data acquisition by pressing Record Histograms again or waiting for 200 measurements to complete the delay values of the auto mea...

Страница 26: ...el might differ from board to board with the step being at a different position Figure 2 26 Histogram for the case the delay value for the board is set correctly Please note the lower panel might diff...

Страница 27: ...of cronoTools and cronoSync can be found in the cronoTools user guide C1 C2 Figure 2 27 Interconnection scheme of a Ndigo5G left and a HPTDC8 PCI right using a Ndigo Extension Board middle 2 6 Perfor...

Страница 28: ...iver After invoking the application a window as shown in Figure 2 29 will appear The calibration procedure is as follows 1 Connect an external pulse signal to the Trigger input The signal should be lo...

Страница 29: ...ata on the card 6 Calibration done The card can only be successfully calibrated if First Bin is in the range of 4 to 16 Empty Bins is less than First Bin 4 at least 10 000 events have been captured a...

Страница 30: ...init parameters init Get a set of default parameters to feed into ndigo init This must always be used to initialize the ndigo init parameter structure ndigo device ndigo init ndigo init parameters par...

Страница 31: ...t sync period Period of the multicard sync pulse Should be set to 4 default when using several Ndigo boards in sync Ignored for single board setups The Ndigo5G has 4 phases relative to the global 10MH...

Страница 32: ...of that magnitude 3 3 2 Structure ndigo static info This structure contains information about the board that does not change during run time It is provided by the function ndigo get static info int s...

Страница 33: ...of the following patterns Bits 3 0 0010 Ndigo5G 10 2 5u 10 0011 Ndigo5G 8 AQ 2 5u 8 0110 Ndigo5G 10 Diff 560pF 10 DIFF 1000 Ndigo5G 8 560pF 8 1010 Ndigo1250M 12 2 2uF 12 Sciex DC 1011 Ndigo5G 10 560pF...

Страница 34: ...10 bit version double sample rate Sample rate This is 1 25e9 2 5e9 or 5 0e9 depending on the current ADC mode sample rate channels 5 0e9 double sample period The period one sample in the data represen...

Страница 35: ...stem configuration 3 3 5 Structure ndigo slow info int size The number of bytes occupied by the structure int version A version number that is increased when the definition of the structure is changed...

Страница 36: ...nstant describing the ADC mode define NDIGO ADC MODE ABCD 0 define NDIGO ADC MODE AC 4 define NDIGO ADC MODE BC 5 define NDIGO ADC MODE AD 6 define NDIGO ADC MODE BD 7 define NDIGO ADC MODE A 8 define...

Страница 37: ...D1 7 define NDIGO TRIGGER TDC 8 define NDIGO TRIGGER GATE 9 define NDIGO TRIGGER BUS0 10 define NDIGO TRIGGER BUS1 11 define NDIGO TRIGGER BUS2 12 define NDIGO TRIGGER BUS3 13 define NDIGO TRIGGER AU...

Страница 38: ...r mapping from ADC value to output value The driver will call this function with a value from 1 to 1 and the function must return the corresponding signed 16 bit value that the board should return for...

Страница 39: ...rigger is ignored and the packet ends after the precursor of the first trigger The retrigger setting is ignored for the timestamp channel ndigo bool t reserved1 Defaults to false Do not change ndigo b...

Страница 40: ...O TRIGGER SOURCE TDC PE 0x01000000 define NDIGO TRIGGER SOURCE GATE PE 0x02000000 define NDIGO TRIGGER SOURCE BUS0 PE 0x04000000 define NDIGO TRIGGER SOURCE BUS1 PE 0x08000000 define NDIGO TRIGGER SOU...

Страница 41: ...trigger even for short gates If not set the input signal must persist for the gate to be created This feature is NOT YET IMPLEMENTED ndigo bool t reserved1 Defaults to false Do not change int start I...

Страница 42: ...x00004000 define NDIGO TRIGGER SOURCE ONE 0x00008000 3 4 5 Structure ndigo extension block This structure configures how the inputs from the optional extension board and signals from the synchronizati...

Страница 43: ...ndigo packet packet Call on a TDC packet to update the timestamp of the packet with a more accurate value If called more than once on a packet the timestamp will be invalid 3 5 1 Input Structure ndig...

Страница 44: ...Set the LED to the selected color No automatic updates are performed int ndigo set led automode ndigo device device int led Let the selected LED be controlled by hardware cronologic GmbH Co KG 39 Ndi...

Страница 45: ...cronologic GmbH Co KG 40 Ndigo5G User Guide...

Страница 46: ...the sources that is enabled for the timestamp channel triggers one of these packets is generated The length field contains the triggers active when this packet was created unsigned char flags define...

Страница 47: ...timestamp Bits are set according to the trigger sources i e bit 0 is set if trigger A0 was active bit 29 is set if trigger BUS3 PE was active Use the NDIGO TRIGGER SOURCE defines to check for the bits...

Страница 48: ...g adc mode NDIGO ADC MODE ABCD 27 28 disable unused t r i g g e r blocks 29 c o n f i g t r i g g e r b l o c k 1 enabled f a l s e 30 c o n f i g t r i g g e r b l o c k 2 enabled f a l s e 31 c o n...

Страница 49: ...cket packet out f i r s t p a c k e t 70 while packet out l a s t p a c k e t 71 int length 0 72 i f packet type NDIGO PACKET TYPE TIMESTAMP ONLY 73 length packet length 74 75 p r i n t f Card 02x Cha...

Страница 50: ...ncl1 Spurious Free Dynamic Range including Harmonics 55 59 dB SFDRexcl1 Spurious Free Dynamic Range excluding Harmonics 55 60 dB SINAD1 Signal to Interference Ratio including Noise and Distortion 47 4...

Страница 51: ...ical Characteristics 6 2 1 Oscillator The Ndigo5G 10 uses a rather expensive oscillator with 25ppb stability 6 2 2 Environmental Conditions for Operation The board is designed to be operated under the...

Страница 52: ...d version Symbol Parameter Min Typical Max Units Vp p Peak to peak input voltage 0 5 V ZP input impedance 50 Analog offset 0 25 0 25 V AC coupled differential analog inputs Symbol Parameter Min Typica...

Страница 53: ...horter than 3m All power supplied to the system must be turned off before installing the board When handling the board adequate measures have to be taken to protect the circuits against electrostatic...

Страница 54: ...on page 47 cronologic GmbH Co KG 49 Ndigo5G User Guide...

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