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MityDSP-L138 Carrier Board Design Guide

March 5, 2014

Page 5 of 17

Document Revision: 1.7

– MityDSP-L138 Revision 4A

Critical Link reserves the right to make corrections, modifications, enhancements, and other changes to this document at any time and without notice.

Pin

Ball

Type I/O Signal

Pin Ball

Type I/O Signal

K18

USB0_DRVVBUS

I/O GP0_4

3V RTC Battery

I/O GP0_3

PWR -

+3.3 V in

PWR -

+3.3 V in

PWR -

+3.3 V in

PWR -

+3.3 V in

PWR -

GND

PWR -

GND

H17 D

I/O SPI1_MISO

I/O GP0_2

G17 D

I/O SPI1_MOSI

I/O GP0_0

H16 D

I/O SPI1_ENA

I/O GP0_8

G19 D

I/O SPI1_CLK

I/O GP0_9

F18

I/O SPI1_SCS[1]

A12

I/O MMCSD0_DAT[7]

Reserved

C11

I/O MMCSD0_DAT[6]

G16 D

I/O I2C0_SCL

E12

I/O MMCSD0_DAT[5]

G18 D

I/O I2C0_SDA

B11

I/O MMCSD0_DAT[4]

F16

I/O UART2_TXD / I2C1_SDA 60

E11

I/O MMCSD0_DAT[3]

F17

I/O UART2_RXD / I2C1_SCL 62

C10

I/O MMCSD0_DAT[2]

PWR -

GND

PWR -

GND

F19

UART1_TXD

A11

I/O MMCSD0_DAT[1]

E18

UART1_RXD

B10

I/O MMCSD0_DAT[0]

E16

MDIO_CLK

A10

I/O MMCSD0_CMD

D17 M

I/O MDIO_D

MMCSD0_CLK

D19 M

MII_RXCLK

MII_TXCLK

C17

MII_RXDV

MII_TXD[3]

D16 M

MII_RXD[0]

MII_TXD[2]

E17

MII_RXD[1]

MII_TXD[1]

D18 M

MII_RXD[2]

MII_TXD[0]

C19

MII_RXD[3]

MII_TXEN

PWR -

GND

PWR -

GND

C18

MII_CRS

MII_COL

C16

MII_RXER

A18

EMA_CS[0]

W15 M

I/O UPP_CHA_START

B15

EMA_OE

V15

VP_CLKIN1

C15

EMA_BA[0]

U18 M

I/O UPP_D[15] / RMII_TXD[1]

A15

EMA_BA[1]

V16

I/O UPP_D[14] / RMII_TXD[0]

C14

EMA_A[0]

100 R14

I/O UPP_D[13] / RMII_TXEN

101

D15 D*

EMA_A[1]

102 W16 M

I/O UPP_D[12] / RMII_RXD[1]

103

B14

EMA_A[2]

104 V17

I/O UPP_D[11] / RMII_RXD[0]

105

D14 M

EMA_A[3]

106 W17 M

I/O UPP_D[10] / RMII_RXER

107

PWR -

GND

108 -

PWR -

GND

109

A14

EMA_A[4]

110 W18 M

I/O UPP_D[9] / RMII_REF_CLK

111

C13

EMA_A[5]

112 W19 M

I/O UPP_D[8] / RMII_CRS_DV

113

E13

EMA_A[6]

114 V18

I/O UPP_D[7]

Содержание MityDSP-6748

Страница 1: ... integrate into an end user embedded system The modules integrate many crucial elements of an embedded system and do so with an established design framework utilizing a common set of core libraries End user design of the application PCB is also intended to be as simple as possible allowing the PCB designer to concentrate on the custom I O interfaces especially analog mixed signal instead of gettin...

Страница 2: ...O and Gigabit Ethernet interfaces provided by the DSP and DDR SDRAM dedicated to the FPGA The 1st generation family of modules the MityDSP and MityDSP XM MityDSP 6711 and MityDSP 6711XM are based on a Texas Instruments TMS3206711 DSP include SDRAM and Flash memories and are interfaced using a 144 pin SO DIMM card edge connector The module integrates a Xilinx Spartan 3 FPGA for implementing require...

Страница 3: ...4A Critical Link reserves the right to make corrections modifications enhancements and other changes to this document at any time and without notice 1 5 Module Dimensions A dimensioned drawing of module is included below in Figure 1 Figure 1 MityDSP L138 MitySOM 1808 MitySOM 1810 MityDSP 6748 Mechanical Drawing ...

Страница 4: ...te that the MityDSP is NOT electrically compatible with the DDR2 socket standard and intermixing modules sockets from the two standards would very possibly cause permanent damage to one or both sides 2 2 Module Pin out The SO DIMM card edge interface contains 4 classes of signals Power PWR Dedicated signals mapped to the processor D Dedicated signals when NAND memory is populated on the module D M...

Страница 5: ... O MMCSD0_DAT 2 63 PWR GND 64 PWR GND 65 F19 M O UART1_TXD 66 A11 M I O MMCSD0_DAT 1 67 E18 M I UART1_RXD 68 B10 M I O MMCSD0_DAT 0 69 E16 M O MDIO_CLK 70 A10 M I O MMCSD0_CMD 71 D17 M I O MDIO_D 72 E9 M O MMCSD0_CLK 73 D19 M I MII_RXCLK 74 D3 M I MII_TXCLK 75 C17 M I MII_RXDV 76 E3 M O MII_TXD 3 77 D16 M I MII_RXD 0 78 E2 M O MII_TXD 2 79 E17 M I MII_RXD 1 80 E1 M O MII_TXD 1 81 D18 M I MII_RXD 2...

Страница 6: ...LKIN2 143 D9 D I O EMA_D 9 144 G3 M I O UPP_CHB_WAIT 145 E10 D I O EMA_D 8 146 G2 M I O UPP_CHB_START 147 D7 D I O EMA_D 7 148 G1 M I O UPP_CHB_CLK 149 C6 D I O EMA_D 6 150 W14 M I VP_CLKIN0 151 PWR GND 152 PWR GND 153 E7 D I O EMA_D 5 154 P4 M I O LCD_D 15 155 B5 D I O EMA_D 4 156 R3 M I O LCD_D 14 157 E8 D I O EMA_D 3 158 R2 M I O LCD_D 13 159 B8 D I O EMA_D 2 160 R1 M I O LCD_D 12 161 A8 D I O ...

Страница 7: ...l low to configure booting from external UART1 RESET_IN I Manual Reset When pulled to GND for a minimum of 1 usec resets the DSP processor SPI1_ I O Serial Peripheral Interface 1 pins These pins are direct connects to the corresponding SPI1_ pins on the OMAP L138 processor The SPI1_ function pins are multiplexed with other functions These include PWM Timers UARTs I2C0 and GPIO For details please r...

Страница 8: ...ns GND N A System Digital Ground EMA_ I O EMIF A pins These pins are direct connects to the corresponding EMA_ pins on the OMAP L138 processor Alternatively these pins can be configured as GPIOs For details please refer to the OMAP L138 Sitara 1808 or TMS320C6748 processor specifications UPP_ I O Universal Parallel Port pins These pins are direct connects to the corresponding UPP_ pins on the OMAP...

Страница 9: ...ultiplexed with other functions These include UPP MMCSD1 and GPIO For details please refer to the OMAP L138 Sitara 1808 or TMS320C6748 processor specifications RESET_OUT I O Reset Output pin This pin is a direct connect to the RESET_OUT pin on the OMAP L138 processor This pin can also be configured as a GPIO For details please refer to the OMAP L138 Sitara 1808 or TMS320C6748 processor specificati...

Страница 10: ... V I3 3 170 300 TBD mA 3 2 Recommended Capacitance All MityDSP L138 family modules include some power supply rail bypass capacitors on board however additional capacitance is recommended on the carrier board to minimize the ripple effect caused by changing load currents It is common practice to place one 10uF tantalum capacitor nearby each power supply pin pair Please note that this is the minimum...

Страница 11: ...ided by the SOC These ports support a variety of synchronous serial communication protocols including TDM and SPI types They can be used for connectivity to a wide array of data converters DACs and ADCs other DSPs and other communications equipment The signals are connected directly to the CPU SOC device pins and are configured for 3 3 V I O logic For more information please consult the DSP device...

Страница 12: ...an RJ 45 style connector RJHSE 5381 or equivalent on the carrier board A connector with integrated magnetics and passives may also be used in place of discrete components All of the SOCs in this family of MityDSP OMAP L138 Sitara 1808 Sitara 1810 and DSP6748 provide support for both standard Media Independent Interface MII and Reduced Media Independent Interface RMII formats The MityDSP L138 famil...

Страница 13: ...nal data bus Instead one port can be configured as output the other as input and both can operate independently and simultaneously The UPP ports are useful in moving data to from CODECs DACs ADCx FPGAs ASICs and other processors Please refer to the SOC datasheets and user guides for more information on the operation of the UPP ports 3 3 13 LCD Controller All MityDSP L138 MitySOM 1808 MitySOM 1810 ...

Страница 14: ...anically compatible but not necessarily footprint compatible with the connector mentioned above Please contact Critical Link for a current list of compatible connector sockets for the module 4 2 Module Clearance All module types use a SO DIMM style main interface connector for electrical and mechanical attachment to the carrier board This style of connector positions the MityDSP module in parallel...

Страница 15: ...etails about utilizing this option Drawing is not to scale Socket Connector MityDSP L138 MitySOM 1808 MitySOM 1810 MityDSP 6748 Module Carrier Board Standoff Hardware Module Center Line 3 3mm 2 8mm 3 0mm Figure 3 Standoff based Hold Down Concept Drawing 4 4 Shock Vibration For customers who are interested in using MityDSP modules in rugged environments the optional mechanical attachment methods di...

Страница 16: ...ets The modules are generally installed at an angle of about 25 to 30 before swinging down to locked position Enclosure designs should accommodate this motion 5 2 Pin out and Routing Care must be taken when routing the SOC high speed interfaces specifically the USB 1 0 and 2 0 OTG ports and the SATA ports Please refer to the specific SOC device specification for guidance related to these pins 5 3 ...

Страница 17: ...Recommended PCB Footprint 6 Revision History Revision Date Description of Changes 1 0 11 September 2010 Initial Revision 1 1 11 November 2011 Added Revision History Added I2C address for PMIC 1 2 13 February 2012 Fix typo in signal names for pins 79 81 and 83 1 3 13 February 2012 Fix typo in pinout table pins 160 170 and 180 were incorrectly numbered 1 4 19 April 2012 Remove erroneous references t...

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