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Critical Link MityDSP-6748, Руководство по конструкции

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MityDSP-L138 Carrier Board Design Guide 

March 5, 2014 

Page 13 of 17 

 

Document Revision: 1.7  

–  MityDSP-L138 Revision 4A 

Critical Link reserves the right to make corrections, modifications, enhancements, and other changes to this document at any time and without notice.

 

3.3.11

 

EMIFA 

All MityDSP-L138, MitySOM-1808, MitySOM-1810, and MityDSP-6748 modules expose the SOC’s External 
Memory Interface-A (EMIFA) bus interface on the SO-DIMM edge connector.  This memory interface bus is 
utilized on-module to support the NAND flash device on chip select 3 (CS3).  The memory interface can be used 
externally to the module for connection to SDRAM, SRAM, flash memories (parallel NAND / NOR), FPGAs, and 
ASICs.  Please refer to the SOC datasheets and user guides for more information on the operation of the EMIF 
bus. 

3.3.12

 

UPP 

All MityDSP-L138, MitySOM-1808, MitySOM-1810, and MityDSP-6748 modules expose the SOC’s Universal 
Parallel Ports.  These two ports each consist of a 8/16-bit wide data bus and synchronization and flow control 
signals.  Each port can be configured as input or output, but they are not intended to be used in applications 
requiring a bi-directional data bus.  Instead, one port can be configured as output, the other as input, and both 
can operate independently and simultaneously.  The UPP ports are useful in moving data to/from CODECs 
(DACs/ADCx), FPGAs, ASICs, and other processors.  Please refer to the SOC datasheets and user guides for more 
information on the operation of the UPP ports. 

3.3.13

 

LCD Controller 

All MityDSP-L138, MitySOM-1808, MitySOM-1810, and MityDSP-6748 modules expose the SOC’s Liquid Crystal 
Display (LCD) Controller port.  This port consists of a 16-bit data bus, and strobes and clocks necessary to 
connect to industry standard LCD module interfaces.  The controller can operate in raster mode, or 
asynchronous memory-mapped mode (LIDD).  Please refer to the SOC datasheets and user guides for more 
information on the operation of the LCD Controller. 

3.3.14

 

Video Port Interface 

All MityDSP-L138, MitySOM-1808, MitySOM-1810, and MityDSP-6748 modules expose the SOC’s Video Port 
Interface (VPIF).  This port consists of two separate data paths – one input and one output.  Each is a 16-bit data 
bus with clock signals.  The ports can be used to move TV/video data into and out of the SOC.  The port pins are 
multiplexed with other functions such as the UPP, RMII, and MMCSD1.  Please refer to the SOC datasheets and 
user guides for more information on the operation of the Video Port Interface. 

Содержание MityDSP-6748

Страница 1: ... integrate into an end user embedded system The modules integrate many crucial elements of an embedded system and do so with an established design framework utilizing a common set of core libraries End user design of the application PCB is also intended to be as simple as possible allowing the PCB designer to concentrate on the custom I O interfaces especially analog mixed signal instead of gettin...

Страница 2: ...O and Gigabit Ethernet interfaces provided by the DSP and DDR SDRAM dedicated to the FPGA The 1st generation family of modules the MityDSP and MityDSP XM MityDSP 6711 and MityDSP 6711XM are based on a Texas Instruments TMS3206711 DSP include SDRAM and Flash memories and are interfaced using a 144 pin SO DIMM card edge connector The module integrates a Xilinx Spartan 3 FPGA for implementing require...

Страница 3: ...4A Critical Link reserves the right to make corrections modifications enhancements and other changes to this document at any time and without notice 1 5 Module Dimensions A dimensioned drawing of module is included below in Figure 1 Figure 1 MityDSP L138 MitySOM 1808 MitySOM 1810 MityDSP 6748 Mechanical Drawing ...

Страница 4: ...te that the MityDSP is NOT electrically compatible with the DDR2 socket standard and intermixing modules sockets from the two standards would very possibly cause permanent damage to one or both sides 2 2 Module Pin out The SO DIMM card edge interface contains 4 classes of signals Power PWR Dedicated signals mapped to the processor D Dedicated signals when NAND memory is populated on the module D M...

Страница 5: ... O MMCSD0_DAT 2 63 PWR GND 64 PWR GND 65 F19 M O UART1_TXD 66 A11 M I O MMCSD0_DAT 1 67 E18 M I UART1_RXD 68 B10 M I O MMCSD0_DAT 0 69 E16 M O MDIO_CLK 70 A10 M I O MMCSD0_CMD 71 D17 M I O MDIO_D 72 E9 M O MMCSD0_CLK 73 D19 M I MII_RXCLK 74 D3 M I MII_TXCLK 75 C17 M I MII_RXDV 76 E3 M O MII_TXD 3 77 D16 M I MII_RXD 0 78 E2 M O MII_TXD 2 79 E17 M I MII_RXD 1 80 E1 M O MII_TXD 1 81 D18 M I MII_RXD 2...

Страница 6: ...LKIN2 143 D9 D I O EMA_D 9 144 G3 M I O UPP_CHB_WAIT 145 E10 D I O EMA_D 8 146 G2 M I O UPP_CHB_START 147 D7 D I O EMA_D 7 148 G1 M I O UPP_CHB_CLK 149 C6 D I O EMA_D 6 150 W14 M I VP_CLKIN0 151 PWR GND 152 PWR GND 153 E7 D I O EMA_D 5 154 P4 M I O LCD_D 15 155 B5 D I O EMA_D 4 156 R3 M I O LCD_D 14 157 E8 D I O EMA_D 3 158 R2 M I O LCD_D 13 159 B8 D I O EMA_D 2 160 R1 M I O LCD_D 12 161 A8 D I O ...

Страница 7: ...l low to configure booting from external UART1 RESET_IN I Manual Reset When pulled to GND for a minimum of 1 usec resets the DSP processor SPI1_ I O Serial Peripheral Interface 1 pins These pins are direct connects to the corresponding SPI1_ pins on the OMAP L138 processor The SPI1_ function pins are multiplexed with other functions These include PWM Timers UARTs I2C0 and GPIO For details please r...

Страница 8: ...ns GND N A System Digital Ground EMA_ I O EMIF A pins These pins are direct connects to the corresponding EMA_ pins on the OMAP L138 processor Alternatively these pins can be configured as GPIOs For details please refer to the OMAP L138 Sitara 1808 or TMS320C6748 processor specifications UPP_ I O Universal Parallel Port pins These pins are direct connects to the corresponding UPP_ pins on the OMAP...

Страница 9: ...ultiplexed with other functions These include UPP MMCSD1 and GPIO For details please refer to the OMAP L138 Sitara 1808 or TMS320C6748 processor specifications RESET_OUT I O Reset Output pin This pin is a direct connect to the RESET_OUT pin on the OMAP L138 processor This pin can also be configured as a GPIO For details please refer to the OMAP L138 Sitara 1808 or TMS320C6748 processor specificati...

Страница 10: ... V I3 3 170 300 TBD mA 3 2 Recommended Capacitance All MityDSP L138 family modules include some power supply rail bypass capacitors on board however additional capacitance is recommended on the carrier board to minimize the ripple effect caused by changing load currents It is common practice to place one 10uF tantalum capacitor nearby each power supply pin pair Please note that this is the minimum...

Страница 11: ...ided by the SOC These ports support a variety of synchronous serial communication protocols including TDM and SPI types They can be used for connectivity to a wide array of data converters DACs and ADCs other DSPs and other communications equipment The signals are connected directly to the CPU SOC device pins and are configured for 3 3 V I O logic For more information please consult the DSP device...

Страница 12: ...an RJ 45 style connector RJHSE 5381 or equivalent on the carrier board A connector with integrated magnetics and passives may also be used in place of discrete components All of the SOCs in this family of MityDSP OMAP L138 Sitara 1808 Sitara 1810 and DSP6748 provide support for both standard Media Independent Interface MII and Reduced Media Independent Interface RMII formats The MityDSP L138 famil...

Страница 13: ...nal data bus Instead one port can be configured as output the other as input and both can operate independently and simultaneously The UPP ports are useful in moving data to from CODECs DACs ADCx FPGAs ASICs and other processors Please refer to the SOC datasheets and user guides for more information on the operation of the UPP ports 3 3 13 LCD Controller All MityDSP L138 MitySOM 1808 MitySOM 1810 ...

Страница 14: ...anically compatible but not necessarily footprint compatible with the connector mentioned above Please contact Critical Link for a current list of compatible connector sockets for the module 4 2 Module Clearance All module types use a SO DIMM style main interface connector for electrical and mechanical attachment to the carrier board This style of connector positions the MityDSP module in parallel...

Страница 15: ...etails about utilizing this option Drawing is not to scale Socket Connector MityDSP L138 MitySOM 1808 MitySOM 1810 MityDSP 6748 Module Carrier Board Standoff Hardware Module Center Line 3 3mm 2 8mm 3 0mm Figure 3 Standoff based Hold Down Concept Drawing 4 4 Shock Vibration For customers who are interested in using MityDSP modules in rugged environments the optional mechanical attachment methods di...

Страница 16: ...ets The modules are generally installed at an angle of about 25 to 30 before swinging down to locked position Enclosure designs should accommodate this motion 5 2 Pin out and Routing Care must be taken when routing the SOC high speed interfaces specifically the USB 1 0 and 2 0 OTG ports and the SATA ports Please refer to the specific SOC device specification for guidance related to these pins 5 3 ...

Страница 17: ...Recommended PCB Footprint 6 Revision History Revision Date Description of Changes 1 0 11 September 2010 Initial Revision 1 1 11 November 2011 Added Revision History Added I2C address for PMIC 1 2 13 February 2012 Fix typo in signal names for pins 79 81 and 83 1 3 13 February 2012 Fix typo in pinout table pins 160 170 and 180 were incorrectly numbered 1 4 19 April 2012 Remove erroneous references t...

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